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[/] [w11/] [tags/] [w11a_V0.61/] [rtl/] [vlib/] [serport/] [tb/] [tb_serport_uart_rx_stim.dat] - Rev 32
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# $Id: tb_serport_uart_rx_stim.dat 91 2007-10-21 18:59:14Z mueller $
#
#
C setting rate=1 -> CLKDIV=0 ------------------------------------------------
.wait 5
.rate 1
C test frame error (send 7,8,9,10 '0' bits, followed by 10 '1' bits)
puls 1 0 11000000 0 7 1 10 -- VAL=1 ERR=0 DAT=11000000
puls 1 0 10000000 0 8 1 10 -- VAL=1 ERR=0 DAT=10000000
puls 1 0 00000000 0 9 1 10 -- VAL=1 ERR=0 DAT=00000000
puls 1 1 00000000 0 10 1 10 -- VAL=1 ERR=1 DAT=00000000
C test 1 stop bits
puls 1 0 00000000 0 9 1 1 -- 1 stop bit VAL=1 ERR=0 DAT=00000000
puls 1 0 11111111 0 1 1 9 -- 1 stop bit VAL=1 ERR=0 DAT=11111111
puls 1 0 00000000 0 9 1 1 -- 1 stop bit VAL=1 ERR=0 DAT=00000000
puls 1 0 11111111 0 1 1 9 -- 1 stop bit VAL=1 ERR=0 DAT=11111111
C test 2 stop bits
puls 1 0 00000000 0 9 1 2 -- 2 stop bit VAL=1 ERR=0 DAT=00000000
puls 1 0 11111111 0 1 1 10 -- 2 stop bit VAL=1 ERR=0 DAT=11111111
puls 1 0 00000000 0 9 1 2 -- 2 stop bit VAL=1 ERR=0 DAT=00000000
puls 1 0 11111111 0 1 1 10 -- 2 stop bit VAL=1 ERR=0 DAT=11111111
C test 3 stop bits
puls 1 0 00000000 0 9 1 3 -- 3 stop bit VAL=1 ERR=0 DAT=00000000
puls 1 0 11111111 0 1 1 11 -- 3 stop bit VAL=1 ERR=0 DAT=11111111
puls 1 0 00000000 0 9 1 3 -- 3 stop bit VAL=1 ERR=0 DAT=00000000
puls 1 0 11111111 0 1 1 11 -- 3 stop bit VAL=1 ERR=0 DAT=11111111
C test 4 stop bits
puls 1 0 00000000 0 9 1 4 -- 4 stop bit VAL=1 ERR=0 DAT=00000000
puls 1 0 11111111 0 1 1 12 -- 4 stop bit VAL=1 ERR=0 DAT=11111111
puls 1 0 00000000 0 9 1 4 -- 4 stop bit VAL=1 ERR=0 DAT=00000000
puls 1 0 11111111 0 1 1 12 -- 4 stop bit VAL=1 ERR=0 DAT=11111111
C test back-to-back data
send 0 00000000
send 0 00000001
send 0 00000010
send 0 00000100
send 0 00001000
send 0 00010000
send 0 00100000
send 0 01000000
send 0 10000000
send 0 11111110
send 0 11111101
send 0 11111011
send 0 11110111
send 0 11101111
send 0 11011111
send 0 10111111
send 0 01111111
send 0 00000000
send 0 11111111
send 0 00000011
send 0 00001100
send 0 00110000
send 0 11000000
C test data with 2 stop bits
send 1 00000000
send 1 00000001
send 1 00000010
send 1 00000100
send 1 00001000
send 1 00010000
send 1 00100000
send 1 01000000
send 1 10000000
send 1 11111110
send 1 11111101
send 1 11111011
send 1 11110111
send 1 11101111
send 1 11011111
send 1 10111111
send 1 01111111
send 1 00000000
send 1 11111111
send 1 00000011
send 1 00001100
send 1 00110000
send 1 11000000
C test data with 3 stop bits
send 2 00000000
send 2 00000001
send 2 00000010
send 2 00000100
send 2 00001000
send 2 00010000
send 2 00100000
send 2 01000000
send 2 10000000
send 2 11111110
send 2 11111101
send 2 11111011
send 2 11110111
send 2 11101111
send 2 11011111
send 2 10111111
send 2 01111111
send 2 00000000
send 2 11111111
send 2 00000011
send 2 00001100
send 2 00110000
send 2 11000000
#
C setting rate=2 -> CLKDIV=1 ------------------------------------------------
.wait 5
.rate 2
C test frame error (send 16,17,18,19,20 '0' bits, followed by 10 '1' bits)
puls 1 0 10000000 0 16 1 10 -- VAL=1 ERR=0 DAT=10000000
puls 1 0 10000000 0 17 1 10 -- VAL=1 ERR=0 DAT=10000000
puls 1 0 00000000 0 18 1 10 -- VAL=1 ERR=0 DAT=00000000
puls 1 0 00000000 0 19 1 10 -- VAL=1 ERR=0 DAT=00000000
puls 1 1 00000000 0 20 1 10 -- VAL=1 ERR=1 DAT=00000000
C test 1 stop bits
puls 1 0 00000000 0 18 1 2 -- 1 stop bit VAL=1 ERR=0 DAT=00000000
puls 1 0 11111111 0 2 1 18 -- 1 stop bit VAL=1 ERR=0 DAT=11111111
puls 1 0 00000000 0 18 1 2 -- 1 stop bit VAL=1 ERR=0 DAT=00000000
puls 1 0 11111111 0 2 1 18 -- 1 stop bit VAL=1 ERR=0 DAT=11111111
C test 2 stop bits
puls 1 0 00000000 0 18 1 4 -- 2 stop bit VAL=1 ERR=0 DAT=00000000
puls 1 0 11111111 0 2 1 20 -- 2 stop bit VAL=1 ERR=0 DAT=11111111
puls 1 0 00000000 0 18 1 4 -- 2 stop bit VAL=1 ERR=0 DAT=00000000
puls 1 0 11111111 0 2 1 20 -- 2 stop bit VAL=1 ERR=0 DAT=11111111
C test 3 stop bits
puls 1 0 00000000 0 18 1 6 -- 3 stop bit VAL=1 ERR=0 DAT=00000000
puls 1 0 11111111 0 2 1 22 -- 3 stop bit VAL=1 ERR=0 DAT=11111111
puls 1 0 00000000 0 18 1 6 -- 3 stop bit VAL=1 ERR=0 DAT=00000000
puls 1 0 11111111 0 2 1 22 -- 3 stop bit VAL=1 ERR=0 DAT=11111111
C test 4 stop bits
puls 1 0 00000000 0 18 1 8 -- 4 stop bit VAL=1 ERR=0 DAT=00000000
puls 1 0 11111111 0 2 1 24 -- 4 stop bit VAL=1 ERR=0 DAT=11111111
puls 1 0 00000000 0 18 1 8 -- 4 stop bit VAL=1 ERR=0 DAT=00000000
puls 1 0 11111111 0 2 1 24 -- 4 stop bit VAL=1 ERR=0 DAT=11111111
C test back-to-back data
send 0 00000000
send 0 00000001
send 0 00000010
send 0 00000100
send 0 00001000
send 0 00010000
send 0 00100000
send 0 01000000
send 0 10000000
send 0 11111110
send 0 11111101
send 0 11111011
send 0 11110111
send 0 11101111
send 0 11011111
send 0 10111111
send 0 01111111
send 0 00000000
send 0 11111111
send 0 00000011
send 0 00001100
send 0 00110000
send 0 11000000
C test data with 2 stop bits
send 1 00000000
send 1 00000001
send 1 00000010
send 1 00000100
send 1 00001000
send 1 00010000
send 1 00100000
send 1 01000000
send 1 10000000
send 1 11111110
send 1 11111101
send 1 11111011
send 1 11110111
send 1 11101111
send 1 11011111
send 1 10111111
send 1 01111111
send 1 00000000
send 1 11111111
send 1 00000011
send 1 00001100
send 1 00110000
send 1 11000000
C test data with 3 stop bits
send 2 00000000
send 2 00000001
send 2 00000010
send 2 00000100
send 2 00001000
send 2 00010000
send 2 00100000
send 2 01000000
send 2 10000000
send 2 11111110
send 2 11111101
send 2 11111011
send 2 11110111
send 2 11101111
send 2 11011111
send 2 10111111
send 2 01111111
send 2 00000000
send 2 11111111
send 2 00000011
send 2 00001100
send 2 00110000
send 2 11000000
#
C setting rate=4 -> CLKDIV=3 ------------------------------------------------
.wait 5
.rate 4
C test back-to-back data
send 0 00000000
send 0 00000001
send 0 00000010
send 0 00000100
send 0 00001000
send 0 00010000
send 0 00100000
send 0 01000000
send 0 10000000
send 0 11111110
send 0 11111101
send 0 11111011
send 0 11110111
send 0 11101111
send 0 11011111
send 0 10111111
send 0 01111111
send 0 00000000
send 0 11111111
send 0 00000011
send 0 00001100
send 0 00110000
send 0 11000000
C test data with 2 stop bits
send 1 00000000
send 1 00000001
send 1 00000010
send 1 00000100
send 1 00001000
send 1 00010000
send 1 00100000
send 1 01000000
send 1 10000000
send 1 11111110
send 1 11111101
send 1 11111011
send 1 11110111
send 1 11101111
send 1 11011111
send 1 10111111
send 1 01111111
send 1 00000000
send 1 11111111
send 1 00000011
send 1 00001100
send 1 00110000
send 1 11000000
#
C setting rate=16 -> CLKDIV=15 -----------------------------------------------
.wait 5
.rate 16
#
C test resonse to start bit runts
puls 0 0 00000000 0 1 1 20 -- will recover fast
puls 0 0 00000000 0 2 1 20 -- "
puls 0 0 00000000 0 3 1 20
puls 0 0 00000000 0 4 1 20
puls 0 0 00000000 0 6 1 20
puls 1 0 11111111 0 10 1 200 -- will be taken as start bit
#
C test back-to-back data
send 0 00000000
send 0 00000001
send 0 00000010
send 0 00000100
send 0 00001000
send 0 00010000
send 0 00100000
send 0 01000000
send 0 10000000
send 0 11111110
send 0 11111101
send 0 11111011
send 0 11110111
send 0 11101111
send 0 11011111
send 0 10111111
send 0 01111111
send 0 00000000
send 0 11111111
send 0 00000011
send 0 00001100
send 0 00110000
send 0 11000000
C test data with 2 stop bits
send 1 00000000
send 1 11110000
send 1 00001111
send 1 11111111
C test data with 3 stop bits
send 2 00000000
send 2 11110000
send 2 00001111
send 2 11111111
C test data with 4 stop bits
send 3 00000000
send 3 11110000
send 3 00001111
send 3 11111111
#
C setting rate=32 -> CLKDIV=31 -----------------------------------------------
.wait 5
.rate 32
C test back-to-back data
send 0 00000000
send 0 00000001
send 0 00000010
send 0 00000100
send 0 00001000
send 0 00010000
send 0 00100000
send 0 01000000
send 0 10000000
send 0 11111110
send 0 11111101
send 0 11111011
send 0 11110111
send 0 11101111
send 0 11011111
send 0 10111111
send 0 01111111
send 0 00000000
send 0 11111111
send 0 00000011
send 0 00001100
send 0 00110000
send 0 11000000
C test data with 2 stop bits
send 1 00000000
send 1 11110000
send 1 00001111
send 1 11111111
C test data with 3 stop bits
send 2 00000000
send 2 11110000
send 2 00001111
send 2 11111111
C test data with 4 stop bits
send 3 00000000
send 3 11110000
send 3 00001111
send 3 11111111
#
C setting rate=32 -> CLKDIV=31 ---- txrate = 31 !! ---------------------------
.wait 5
.rate 32
.xrate 31
C test back-to-back data
send 0 00000000
send 0 00000001
send 0 00000010
send 0 00000100
send 0 00001000
send 0 00010000
send 0 00100000
send 0 01000000
send 0 10000000
send 0 11111110
send 0 11111101
send 0 11111011
send 0 11110111
send 0 11101111
send 0 11011111
send 0 10111111
send 0 01111111
send 0 00000000
send 0 11111111
send 0 00000011
send 0 00001100
send 0 00110000
send 0 11000000
C test data with 2 stop bits
send 1 00000000
send 1 11110000
send 1 00001111
send 1 11111111
C test data with 3 stop bits
send 2 00000000
send 2 11110000
send 2 00001111
send 2 11111111
C test data with 4 stop bits
send 3 00000000
send 3 11110000
send 3 00001111
send 3 11111111
#
C setting rate=32 -> CLKDIV=31 ---- txrate = 33 !! ---------------------------
.wait 5
.rate 32
.xrate 33
C test back-to-back data
send 0 00000000
send 0 00000001
send 0 00000010
send 0 00000100
send 0 00001000
send 0 00010000
send 0 00100000
send 0 01000000
send 0 10000000
send 0 11111110
send 0 11111101
send 0 11111011
send 0 11110111
send 0 11101111
send 0 11011111
send 0 10111111
send 0 01111111
send 0 00000000
send 0 11111111
send 0 00000011
send 0 00001100
send 0 00110000
send 0 11000000
C test data with 2 stop bits
send 1 00000000
send 1 11110000
send 1 00001111
send 1 11111111
C test data with 3 stop bits
send 2 00000000
send 2 11110000
send 2 00001111
send 2 11111111
C test data with 4 stop bits
send 3 00000000
send 3 11110000
send 3 00001111
send 3 11111111
#
C setting rate=27 -> CLKDIV=25 ---- txrate = 26 !! ---------------------------
.wait 5
.rate 27
.xrate 26
C test back-to-back data
send 0 00000000
send 0 00000001
send 0 00000010
send 0 00000100
send 0 00001000
send 0 00010000
send 0 00100000
send 0 01000000
send 0 10000000
send 0 11111110
send 0 11111101
send 0 11111011
send 0 11110111
send 0 11101111
send 0 11011111
send 0 10111111
send 0 01111111
send 0 00000000
send 0 11111111
send 0 00000011
send 0 00001100
send 0 00110000
send 0 11000000
C test data with 2 stop bits
send 1 00000000
send 1 11110000
send 1 00001111
send 1 11111111
C test data with 3 stop bits
send 2 00000000
send 2 11110000
send 2 00001111
send 2 11111111
C test data with 4 stop bits
send 3 00000000
send 3 11110000
send 3 00001111
send 3 11111111
#
C setting rate=27 -> CLKDIV=27 ---- txrate = 28 !! ---------------------------
.wait 5
.rate 27
.xrate 28
C test back-to-back data
send 0 00000000
send 0 00000001
send 0 00000010
send 0 00000100
send 0 00001000
send 0 00010000
send 0 00100000
send 0 01000000
send 0 10000000
send 0 11111110
send 0 11111101
send 0 11111011
send 0 11110111
send 0 11101111
send 0 11011111
send 0 10111111
send 0 01111111
send 0 00000000
send 0 11111111
send 0 00000011
send 0 00001100
send 0 00110000
send 0 11000000
C test data with 2 stop bits
send 1 00000000
send 1 11110000
send 1 00001111
send 1 11111111
C test data with 3 stop bits
send 2 00000000
send 2 11110000
send 2 00001111
send 2 11111111
C test data with 4 stop bits
send 3 00000000
send 3 11110000
send 3 00001111
send 3 11111111
#
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