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[/] [w11/] [tags/] [w11a_V0.7/] [rtl/] [make_ise/] [syn_s6_speed.opt] - Rev 33
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FLOWTYPE = FPGA_SYNTHESIS;
#
# $Id: syn_s6_speed.opt 537 2013-10-06 09:06:23Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2013-10-05 537 1.2 define all, use -opt_level=2, -shreg_min_size=3
# 2012-02-05 456 1.1 use $top_entity variable for -top attribute
# 2011-08-13 405 1.0 Initial version
#
# Derived from ISE xst_mixed.opt
#
# ----------------------------------------------------------------------------
# Options for XST
#
Program xst
-ifn <design>_xst.scr; # input XST script file
-ofn <design>_xst.log; # output XST log file
-intstyle xflow; # Message Reporting Style
#
# ParamFile lists the XST Properties that can be set by the user.
#
ParamFile: <design>_xst.scr
"run";
#
# Global Synthesis Options
#
"-ifn <synthdesign>"; # Input/Project File Name
"-ifmt mixed"; # Input Format (Verilog and VHDL)
"-ofn <design>"; # Output File Name
"-ofmt ngc"; # Output File Format
"-top $top_entity"; # Top Design Name
"-p <partname>"; # Target Device
"-uc <design>.xcf"; # Constraint File name
"-opt_mode SPEED"; # Optimization Criteria # AREA or SPEED
"-opt_level 2"; # Optimization Effort Criteria def=1 !
"-power NO"; # def
"-iuc NO"; # def
"-keep_hierarchy No"; # def
"-netlist_hierarchy As_Optimized";# def
"-rtlview No"; # def=yes if from ISE
"-glob_opt AllClockNets"; # likely def
"-read_cores YES"; # def (irrelevant)
"-write_timing_constraints NO"; # def
"-cross_clock_analysis NO"; # def
"-hierarchy_separator /"; # ?
"-bus_delimiter <>"; # def
"-case Maintain"; # def
"-slice_utilization_ratio 100"; # ?
"-bram_utilization_ratio 100"; # ?
"-dsp_utilization_ratio 100"; # ?
"-lc Auto"; # def
"-reduce_control_sets Auto"; # def
"-fsm_extract YES"; # def
"-fsm_encoding Auto"; # def
"-safe_implementation No"; # def
"-fsm_style LUT"; # def
"-ram_extract Yes"; # def
"-ram_style Auto"; # def
"-rom_extract Yes"; # def
"-rom_style Auto"; # def
"-shreg_extract YES"; # def
"-shreg_min_size 3"; # default is 2 !!
"-auto_bram_packing NO"; # def
"-resource_sharing YES"; # def
"-async_to_sync NO"; # def
"-use_dsp48 Auto"; # def
"-iobuf YES"; # def
"-max_fanout 100000"; # def
"-bufg 16"; # def (for S-6)
"-register_duplication YES"; # def
"-register_balancing No"; # def
"-optimize_primitives NO"; # def
"-use_clock_enable Auto"; # def
"-use_sync_set Auto"; # def
"-use_sync_reset Auto"; # def
"-iob Auto"; # ?
"-equivalent_register_removal YES"; # def
"-slice_utilization_ratio_maxmargin 5"; # ?
#
# The following are HDL Options
#
End ParamFile
End Program xst
#