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## $Id: sys_tst_fx2loop_ic_n3.ucf_cpp 556 2014-05-29 19:01:39Z mueller $
##
## Revision History: 
## Date         Rev Version  Comment
## 2013-10-13   540   1.1    add pad->clk and fx2 cdc constraints
## 2012-04-09   461   1.0    Initial version
##

NET "I_CLK100" TNM_NET = "I_CLK100";
TIMESPEC "TS_I_CLK100" = PERIOD "I_CLK100" 10.0 ns HIGH 50 %;
OFFSET =  IN 10 ns BEFORE "I_CLK100";
OFFSET = OUT 20 ns  AFTER "I_CLK100";

## constrain pad->net clock delay
NET CLK TNM = TNM_CLK;
TIMESPEC TS_PAD_CLK=FROM PADS(I_CLK100) TO TNM_CLK 10 ns;
NET I_FX2_IFCLK_BUFGP TNM = TNM_IFCLK;
TIMESPEC TS_PAD_IFCLK=FROM PADS(I_FX2_IFCLK) TO TNM_IFCLK 10 ns;

## constrain async pad->pad delays
TIMEGRP TG_SLOW_INS  = PADS(I_RXD);
TIMEGRP TG_SLOW_OUTS = PADS(O_TXD);
TIMESPEC TS_ASYNC_PADS=FROM TG_SLOW_INS TO TG_SLOW_OUTS 10 ns;

## FX2 controller specific constraints
##   constrain cdc path in fifos and reset 
TIMESPEC TS_CDC_FIFO = 
   FROM FFS(*FIFO/GC?/GRAY_*.CNT/R_DATA* 
            *FIFO/R_REG?_rst?   
            *FIFO/R_REG?_rst?_s)
   TO   FFS(*FIFO/R_REG?_?addr_c*
            *FIFO/R_REG?_rst?_c 
            *FIFO/R_REG?_rst?_sc)
   5 ns DATAPATHONLY;

##   constrain cdc path in monitor
TIMESPEC TS_CDC_FX2MONI = FROM FFS 
                          TO   FFS(FX2_CNTL*/R_MONI_C*) 5 ns DATAPATHONLY;

##
## std board
##
#include "bplib/nexys3/nexys3_pins.ucf"
##
## FX2 interface
##
#include "bplib/nexys3/nexys3_pins_fx2.ucf"
#include "bplib/nexys3/nexys3_time_fx2_ic.ucf"