OpenCores
URL https://opencores.org/ocsvn/w11/w11/trunk

Subversion Repositories w11

[/] [w11/] [tags/] [w11a_V0.7/] [rtl/] [sys_gen/] [tst_rlink/] [nexys2/] [sys_tst_rlink_n2.mfset] - Rev 12

Go to most recent revision | Compare with Previous | Blame | View Log

# $Id: sys_tst_rlink_n2.mfset 406 2011-08-14 21:06:44Z mueller $
#
# ----------------------------------------------------------------------------
[xst]
INFO:.*Mux is complete : default of case is discarded

Node <HIO/R_REGS.swieff_[1-7]> of sequential type is unconnected
Node <HIO/R_REGS.swi_[1-7]> of sequential type is unconnected
Node <HIO/R_REGS.btneff_[0-5]> of sequential type is unconnected
Node <HIO/R_REGS.btn_[0-5]> of sequential type is unconnected

Unconnected output port 'LOCKED' of component 'dcm_sp_sfs'
Unconnected output port 'OFIFO_SIZE' of component 'rlink_base'
Unconnected output port 'DOA' of component 'ram_1swar_1ar_gen'
Unconnected output port 'DOB' of component 'ram_2swsr_wfirst_gen'

Input <I_MEM_WAIT> is never used
Input <RB_MREQ.din<\d+:\d+>> is never used
Input <RB_MREQ.init> is never used
Input <RB_MREQ.aval> is never used
Input <RB_MREQ.re> is never used

Signal <L_DO<17:16>> is assigned but never used
Signal <FIFO_SIZE> is assigned but never used
Signal <SIZE<1:0>> is assigned but never used
ignal <RL_MONI.lamp> is assigned but never used
Signal <RL_MONI.eop> is assigned but never used
Signal <RL_MONI.attn> is assigned but never used
Signal <RB_LAM_TEST<1:0>> is assigned but never used
Signal <SWI<7:1>> is assigned but never used
Signal <STAT<7:2>> is assigned but never used
Signal <RL_SER_MONI.rxerr> is assigned but never used
Signal <RL_SER_MONI.rxdrop> is assigned but never used
Signal <RL_SER_MONI.abdone> is assigned but never used
Signal <BTN> is assigned but never used

FF/Latch <R_REGS.ledin_2> in Unit <sn_humanio_rbus> is equivalent
FF/Latch <R_REGS.rbre> in Unit <rlink_core> is equivalent

FF/Latch <R_REGS.ledin_2> has a constant value of 0
FF/Latch <R_REGS.ucnt_6> has a constant value of 0

#
# ----------------------------------------------------------------------------
[tra]

#
# ----------------------------------------------------------------------------
[map]
The signal <I_MEM_WAIT_IBUF> is incomplete
Logical network I_MEM_WAIT_IBUF has no load
INFO:.*

#
# ----------------------------------------------------------------------------
[par]
The signal I_MEM_WAIT_IBUF has no load
There are 1 loadless signals in this design
#
# ----------------------------------------------------------------------------
[bgn]
Spartan-3 1200E and 1600E devices do not support bitstream
The signal <I_MEM_WAIT_IBUF> is incomplete

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.