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# $Id: w11a_tb_guide.txt 745 2016-03-18 22:10:34Z mueller $

Note: - Ghdl is used to all functional simulations
      - Optionally Vivado xsim can be used (with some limitations)
      - For post synthesis or post implementation simulations either
        Ghdl or Vivado xsim (with some limitations) can be used.
      - ISE isim is also available, but considered legacy support

Guide to running w11a test benches

  Table of content:
  
  1. Unit tests benches
  2. Available unit tests benches
  3. System tests benches
  4. Available system tests benches


1. Unit tests benches -----------------------------------------------------

   All unit test benches have the same simple structure:

   - a stimulus process reads test patterns as well as the expected
     responses from a stimulus file

   - the responses are checked in very simple cases by the stimulus process,
     in general by a monitoring process

   - the test bench produces a comprehensive log file. For each checked
     response the line contains the word "CHECK" and either an "OK" or a
     "FAIL", in the later case in general with an indication of whats wrong.
     Other unexpected behaviour, like timeouts, will also result in a line
     containing the word "FAIL".

   - at the end a line with the word "DONE" is printed.

   - the test bench is run like

       tbw <testbenchname> [stimfile] | tee <logfile> | egrep "(FAIL|DONE)"

     where 
       - 'tbw' is a small perl script setting up a symbolic link to the
         stimulus file, the default extracted from the file tbw.dat, if
         an optional file name is give this one will be used instead.
       - 'tee' ensures that the full log is saved
       - 'egrep' filters FAIL and DONE lines, a successful run will
         produce a single DONE line

   - Most tests can be run against 
       - the functional model

       - gate level models at three stages (vivado flow)
         - the post synthesis model     (from *_syn.dcp)
         - the post optimization model  (from *_opt.dcp)
         - the post routing  model      (from *_rou.dcp)
         This is simply done using
           make <testbench>_ssim       for post-synthesis
           make <testbench>_osim       for post-optimization
           make <testbench>_tsim       for post-routing

       - gate level models at three stages (ISE flow)
         - the post-xst model   (produced by netgen from ngc xst output)
         - the post-map model   (produced by netgen from ncd ngdbuild output)
         - the post-par model   (produced by netgen from ncd par output)
         This is simply done using
           make <testbench>_ssim       for post-xst
           make <testbench>_fsim       for post-map
           make <testbench>_tsim       for post-par

     All the rest is handled by the build environment.
     An example of a post-synthesis model is given for the w11a core test.

   - for convenience a wrapper script 'tbrun_tbw' is used to generate the 
     tbw|tee|egrep pipe. This script also checks with 'make' whether the
     test bench is up-to-date or must be (re)-compiled.

2. Available unit tests benches -------------------------------------------

   In the following the available tests are listed with their tbrun_tbw which
     - will call 'make' to build them
     - and create the pipe setup to run them
   and the expected output (the run time measured on a 3 GHz system)

   - serport receiver test
     cd $RETROBASE/rtl/vlib/serport/tb
     tbrun_tbw tb_serport_uart_rx 
     -> 1269955.0 ns  63488: DONE 
     -> real 0m0.444s   user 0m0.453s   sys  0m0.007s

   - serport receiver/transmitter test
     tbrun_tbw tb_serport_uart_rxtx
     -> 52335.0 ns   2607: DONE 
     -> real 0m0.074s   user 0m0.077s   sys  0m0.010s

   - serport autobauder test
     tbrun_tbw tb_serport_autobaud
     -> 367475.0 ns  18364: DONE 
     -> real 0m0.247s   user 0m0.258s   sys  0m0.007s

 
   - 9 bit comma,data to Byte stream converter test
     cd $RETROBASE/rtl/vlib/comlib/tb
     tbrun_tbw tb_cdata2byte
     -> 7261.0 ns    354: DONE 
     -> real 0m0.042s   user 0m0.042s   sys  0m0.019s

   - rlink core test

     cd $RETROBASE/rtl/vlib/rlink/tb
     tbrun_tbw tb_rlink_direct
     -> 78975.0 ns   3939: DONE 
     -> real 0m0.225s   user 0m0.226s   sys  0m0.025s

   - rlink core test via serial port interface

     cd $RETROBASE/rtl/vlib/rlink/tb
     tbrun_tbw --lsuf stim2_dsim   tb_rlink_sp1c tb_rlink_sp1c_stim.dat
     -> 27595.0 ns   1370: DONE 
     -> real 0m0.098s   user 0m0.111s   sys  0m0.007s

     tbrun_tbw --lsuf stim1_dsim   tb_rlink_sp1c tb_rlink_stim.dat
     -> 420295.0 ns  21005: DONE 
     -> real 0m0.942s   user 0m0.947s   sys  0m0.012s

   - w11a core test (using behavioural model)

     cd $RETROBASE/rtl/w11a/tb
     tbrun_tbw tb_pdp11core
     -> 225355.0 ns  61258: DONE 
     -> real 0m6.280s   user 0m6.284s   sys  0m0.018s

   - w11a core test (using Vivado post-synthesis model)

     tbrun_tbw tb_pdp11core_ssim
     -> 225355.0 ns  61258: DONE 
     -> real 2m4.138s   user 2m4.063s   sys  0m0.050s

   - s3board sram controller test 

     cd $RETROBASE/rtl/bplib/s3board/tb
     tbrun_tbw tb_s3_sram_memctl
     -> 5015.0 ns    241: DONE 
     -> real 0m0.107s   user 0m0.055s   sys  0m0.020s

   - nexys2/nexys3 cram controller test 

     cd $RETROBASE/rtl/bplib/nxcramlib/tb
     tbrun_tbw tb_nx_cram_memctl_as
     -> 24272.5 ns   1204: DONE 
     -> real 0m0.189s   user 0m0.149s   sys  0m0.055s

3. System tests benches ---------------------------------------------------

   The system tests allow to verify to verify a full system design.
   In this case vhdl test bench code contains
     - (simple) models of the memories used on the FPGA boards
     - drivers for the rlink connection (currently just serialport)
     - code to interface the rlink data stream to a UNIX 'named pipe',
       implemented with a C routine which is called via VHPI from VHDL.
   This way the whole ghdl simulation can be controlled via a di-directional
   byte stream. 

   The rlink backend process can connect either via a named pipe to a ghdl 
   simulation, or via a serial port to a FPGA board. This way the same tests 
   can be executed in simulation and on real hardware.

4. Available system tests benches -----------------------------------------

4a. serport tester ---------------------------------------------------

   The sys_tst_serloop design is a test target for validating the serial
   link UART stack. Send and receive throughput as well as loop-back tests
   are supported

   - sys_tst_serloop_s3 test bench

     cd $RETROBASE/rtl/sys_gen/tst_serloop/s3board/tb
     tbrun_tbw tb_tst_serloop_s3
     -> 301353.3 ns  18068: DONE 
     -> real 0m0.765s   user 0m0.781s   sys  0m0.013s

   - sys_tst_serloop_n2 test bench

     cd $RETROBASE/rtl/sys_gen/tst_serloop/nexys2/tb
     tbrun_tbw tb_tst_serloop1_n2
     -> 361560.0 ns  18068: DONE
     -> real 0m0.994s   user 0m0.991s   sys  0m0.022s

     tbrun_tbw tb_tst_serloop2_n2
     -> 304353.3 ns  18248: DONE
     -> real 0m1.543s   user 0m1.561s   sys  0m0.007s

   - sys_tst_serloop_n3 test bench

     cd $RETROBASE/rtl/sys_gen/tst_serloop/nexys3/tb
     tbrun_tbw tb_tst_serloop1_n3
     -> 361560.0 ns  18068: DONE
     -> real 0m0.740s   user 0m0.755s   sys  0m0.012s

4b. rlink tester -----------------------------------------------------

   The sys_tst_rlink design is a test target for validating the rlink and 
   rbus functionality at all levels.

   - Artix based systems

     - sys_tst_rlink_arty test bench
  
       cd $RETROBASE/rtl/sys_gen/tst_rlink/arty/tb
       tbrun_tbwrri --hxon --pack tst_rlink   tb_tst_rlink_arty \
           "tst_rlink::setup"  "tst_rlink::test_all"
       -> 764400.0 ns  76419: DONE
       -> real 0m9.323s   user 0m9.233s   sys  0m0.080s

     - sys_tst_rlink_b3 test bench
  
       cd $RETROBASE/rtl/sys_gen/tst_rlink/basys3/tb
       tbrun_tbwrri --hxon --pack tst_rlink   tb_tst_rlink_b3 \
           "tst_rlink::setup"  "tst_rlink::test_all"
       -> 763900.0 ns  76369: DONE
       -> real 0m6.804s   user 0m6.696s   sys  0m0.085s
  
     - sys_tst_rlink_n4 test bench
  
       cd $RETROBASE/rtl/sys_gen/tst_rlink/nexys4/tb
       tbrun_tbwrri --pack tst_rlink   tb_tst_rlink_n4 \
           "tst_rlink::setup"  "tst_rlink::test_all"
       -> 758010.0 ns  75780: DONE
       -> real 0m10.198s   user 0m10.081s   sys  0m0.104s


   - Spartan based systems

     - sys_tst_rlink_n3 test bench
  
       cd $RETROBASE/rtl/sys_gen/tst_rlink/nexys3/tb
       tbrun_tbwrri --fusp --pack tst_rlink   tb_tst_rlink_n3 \
           "tst_rlink::setup"  "tst_rlink::test_all"
       -> 763770.0 ns  76356: DONE
       -> real 0m5.955s   user 0m5.834s   sys  0m0.094s

     - sys_tst_rlink_n2 test bench
  
       cd $RETROBASE/rtl/sys_gen/tst_rlink/nexys2/tb
       tbrun_tbwrri --fusp --pack tst_rlink   tb_tst_rlink_n2 \
           "tst_rlink::setup"  "tst_rlink::test_all"
       -> 1526860.0 ns  76332: DONE
       -> real 0m8.607s   user 0m8.448s   sys  0m0.150s
  
     - sys_tst_rlink_s3 test bench
  
       cd $RETROBASE/rtl/sys_gen/tst_rlink/s3board/tb
       tbrun_tbwrri --fusp --pack tst_rlink   tb_tst_rlink_s3 \
           "tst_rlink::setup"  "tst_rlink::test_all" 
       -> 1526540.0 ns  76317: DONE
       -> real 0m5.650s   user 0m5.571s   sys  0m0.052s

4c. rlink tester, Cypress FX2 based version --------------------------

   The sys_tst_rlink_cuff design is a test target for validating the rlink and 
   rbus functionality at all levels over the Cypress FX2 USB interface which
   is provided by the Nexys2 abd Nexys3 boards.

   - sys_tst_rlink_cuff_ic_n3 test bench

     cd $RETROBASE/rtl/sys_gen/tst_rlink_cuff/nexys3/ic/tb
     tbrun_tbwrri --cuff --pack tst_rlink   tb_tst_rlink_cuff_ic_n3 \
         "tst_rlink::setup"  "tst_rlink::test_all"
     -> 440440.0 ns  44023: DONE
     -> real 0m4.062s   user 0m3.922s   sys  0m0.111s

   - sys_tst_rlink_cuff_ic_n2 test bench

     cd $RETROBASE/rtl/sys_gen/tst_rlink_cuff/nexys2/ic/tb
     tbrun_tbwrri --cuff --pack tst_rlink   tb_tst_rlink_cuff_ic_n2 \
         "tst_rlink::setup"  "tst_rlink::test_all"
     -> 466940.0 ns  23336: DONE
     -> real 0m2.831s   user 0m2.696s   sys  0m0.101s

4d. w11a systems -----------------------------------------------------

   The stimulus file used in the w11a core test can be executed in the full
   system context with the following commands. Note that the cycle number 
   printed in the DONE line can now vary slightly because the response time of
   the rlink backend process and thus scheduling of backend vs. ghdl process
   can affect the result.

   For convenience a wrapper script 'tbrun_tbwrri' is used to generate the 
   required quite long ti_rri command. Like for 'tbrun_tbw' the script also
   checks with 'make' whether the test bench is up-to-date or must be 
   (re)-compiled.

   - Artix based systems

       cd $RETROBASE/rtl/sys_gen/w11a/nexys4/tb
       tbrun_tbwrri --pack rw11  tb_w11a_n4 \
           "rw11::setup_cpu" \
           "rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat"
       -> 6681310.0 ns 534488: DONE
       -> real 1m26.253s   user 1m26.139s   sys  0m0.430s

   - Spartan based systems
     - sys_w11a_n3 test bench
  
       cd $RETROBASE/rtl/sys_gen/w11a/nexys3/tb
       tbrun_tbwrri --cuff --pack rw11  tb_w11a_n3 \
           "rw11::setup_cpu" \
           "rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat"
       -> 3614866.2 ns 231338: DONE
       -> real 0m47.290s   user 0m46.975s   sys  0m0.537s

     - sys_w11a_n2 test bench
  
       cd $RETROBASE/rtl/sys_gen/w11a/nexys2/tb
       tbrun_tbwrri --cuff --pack rw11  tb_w11a_n2 \
           "rw11::setup_cpu" \
           "rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat"
       -> 4007500.0 ns 200364: DONE 
       -> real 0m43.803s   user 0m43.698s   sys  0m0.400s
  
     - sys_w11a_s3 test bench
  
       cd $RETROBASE/rtl/sys_gen/w11a/s3board/tb
       tbrun_tbwrri --fusp --pack rw11  tb_w11a_s3 \
           "rw11::setup_cpu" \
           "rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat"
       -> 10526060.0 ns 526293: DONE
       -> real 1m13.659s   user 1m13.467s   sys  0m0.431s
  

   A new, modular w11a test bench is under construction. So far it is very
   incomplete. This very preliminary version can be executed with

   - sys_w11a_n2 test bench

     cd $RETROBASE/rtl/sys_gen/w11a/nexys2/tb
     tbrun_tbwrri  --cuff --lsuf tbench_dsim --pack rw11  tb_w11a_n2 \
        "rw11::setup_cpu" "rw11::tbench @cpu_all.dat"
     -> 3280220.0 ns 164000: DONE
     -> real 0m30.190s   user 0m30.843s   sys  0m0.577s

     tbrun_tbwrri --cuff --lsuf tbench_dsim --pack rw11  tb_w11a_n2 \
        "rw11::setup_cpu" "rw11::tbench @dev_all.dat"
     -> 1387300.0 ns  69354: DONE
     -> real 0m14.298s   user 0m14.314s   sys  0m0.240s