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[/] [w11/] [tags/] [w11a_V0.74/] [rtl/] [w11a/] [tb/] [tb_pdp11core_stim.dat] - Rev 38
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# $Id: tb_pdp11core_stim.dat 716 2015-12-22 21:44:33Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2015-12-22 716 2.7 comment out test 20.13 (fails since r708)
# 2015-05-08 675 2.6 start/stop/suspend overhaul
# 2014-12-26 621 2.5 adopt wmembe,ribr,wibr emulation to new 4k window
# 2014-12-20 614 2.4 adopted to rlink v4
# 2014-07-13 569 2.3 after ECO-026: correct test 31.1 wrong V=1 cases
# correct test 37.2: 2 V=1 cases have regs now updated
# 2010-06-20 308 2.2.1 add wibrb, ribr, wibr based tests
# 2010-06-13 305 2.2 adopt to new rri address and function semantics
# 2009-11-22 252 2.1.14 change SSR0 expects, adapt to ECO-021.
# 2009-05-02 211 2.1.13 add nop after spl in pirq test, 11/70 spl now !!
# 2008-08-29 163 2.1.12 add wtlam to harvest attn after sto in test 13
# 2008-04-27 139 2.1.11 adapt expected ssr1 after mtpi/d after ECO-009 fix
# 2008-03-15 125 2.1.10 exclude some tests from simh ([[off/on]]
# 2008-03-09 124 2.1.9 fixed addr-mode in code 34, shifted 47+50
# 2008-03-02 121 2.1.8 add meory access error tests
# add Code 13, testing WAIT and bwm/brm while CPU runs
# 2008-02-24 119 2.1.7 add tests for lah,rps,wps; use rps,wps
# use 22bit mode for nxm test (now needed!)
# 2008-02-23 118 2.1.6 for nxm tests use mmu and page below i/o-page
# in code 35 use access to 160000 to test trap
# 2007-09-23 84 2.1.5 use .reset to make it re-executable
# 2007-09-16 83 2.1.4 clear CPUERR in beginning of test 20 {runs in FPGA}
# 2007-09-02 79 2.1.3 add .mode command (for pi_rri use)
# 2007-08-25 75 2.1.2 add .cpmon/.rpmon (for use with rri)
# 2007-08-16 74 2.1.1 adapt to changed LAM handling
# 2007-08-12 73 2.1 use wtgo (revised conv_stim)
# 2007-08-03 71 2.0 convert to command mode with conv_stim
# 2007-07-08 65 1.2 removed 1st 'delay' parameter; use .to_(cmd|stp|go)
# 2007-06-10 51 1.1 consolidate w11a test bench
# 2007-05-13 29 1.0 initial version (imported)
#
.mode pdpcp
.tocmd 50
.tostp 100
.togo 5000
.rlmon 0
.rbmon 0
.scntl 13 0
#
.reset
.wait 10
.anena 1
#
C "Code 0" Some elementary initial tests
C write registers
#
wr0 000001 -- set r0,..,r7
wr1 000101 --
wr2 000201 --
wr3 000301 --
wr4 000401 --
wr5 000501 --
wsp 000601 --
wpc 000701 --
#
C read registers
#
rr0 d=000001 -- ! r0
rr1 d=000101 -- ! r1
rr2 d=000201 -- ! r2
rr3 d=000301 -- ! r3
rr4 d=000401 -- ! r4
rr5 d=000501 -- ! r5
rsp d=000601 -- ! sp
rpc d=000701 -- ! pc
#
C write memory
#
wal 002000 -- write mem(2000,...,2006)
bwm 4
007700 --
007710 --
007720 --
007730 --
#
C read memory
#
wal 002000
brm 4
d=007700 -- ! mem(2000)
d=007710 -- ! mem(2002)
d=007720 -- ! mem(2004)
d=007730 -- ! mem(2006)
#
C write/read PSW via various mechanisms
C via wps/rps
#
wps 000017
rps d=000017
wps 000000
rps d=000000
#
C via 16bit cp addressing (wal 177776)
#
wal 177776
wm 000017 -- set all cc flags in psw
rm d=000017 -- ! psw
rps d=000017
wm 000000 -- clear psw
rm d=000000 -- ! psw
rps d=000000
#
C via 22bit cp addressing (wal 177776; wah 177)
#
wal 177776
wah 000177
wm 000017 -- set all cc flags in psw
rm d=000017 -- ! psw
rps d=000017
wm 000000 -- clear psw
rm d=000000 -- ! psw
rps d=000000
#
C via ibr (ibrb 177700)
#
wibr 177776 000017 -- set all cc flags in psw
ribr 177776 d=000017 -- ! psw
rps d=000017
wibr 177776 000000 -- set all cc flags in psw
ribr 177776 d=000000 -- ! psw
rps d=000000
#
C write register set 1, sm,um stack
#
wps 004000 -- psw: cm=kernel, set=1
wr0 010001 -- set r0,..,r5 [[r10]]
wr1 010101 -- [[r11]]
wr2 010201 -- [[r12]]
wr3 010301 -- [[r13]]
wr4 010401 -- [[r14]]
wr5 010501 -- [[r15]]
wps 044000 -- psw: cm=super(01),set=1
wsp 010601 -- set ssp [[ssp]]
wps 144000 -- psw: cm=user(11),set=1
wsp 110601 -- set usp [[usp]]
#
C read all registers set 0/1, km,sm,um stack
#
wps 000000 -- psw: cm=kernel(00),set=0
rr0 d=000001 -- ! r0
rr1 d=000101 -- ! r1
rr2 d=000201 -- ! r2
rr3 d=000301 -- ! r3
rr4 d=000401 -- ! r4
rr5 d=000501 -- ! r5
rsp d=000601 -- ! ksp
rpc d=000701 -- ! pc
wps 040000 -- psw: cm=super(01),set=0
rsp d=010601 -- ! ssp [[ssp]]
wps 140000 -- psw: cm=user(11),set=0
rsp d=110601 -- ! usp [[usp]]
wps 144000 -- psw: cm=user(11),set=1
rr0 d=010001 -- ! r0 [[r10]]
rr1 d=010101 -- ! r1 [[r11]]
rr2 d=010201 -- ! r2 [[r12]]
rr3 d=010301 -- ! r3 [[r13]]
rr4 d=010401 -- ! r4 [[r14]]
rr5 d=010501 -- ! r5 [[r15]]
#
C write IB space: MMU SAR supervisor mode (16 bit regs)
#
wal 172240 -- set first three SM I space address regs
bwm 3
012340
012342
012344
#
C read IB space: MMU SAR supervisor mode (16 bit regs)
#
wal 172240 -- ! verify first three SM I space address regs
brm 3
d=012340
d=012342
d=012344
#
C read IB space via ibr: MMU SAR supervisor mode (16 bit regs)
#
ribr 172240 d=012340
ribr 172242 d=012342
ribr 172244 d=012344
#
C byte write IB space via ibr: MMU SAR supervisor mode (16 bit regs)
#
wmembe 101 -- write low byte (set sticky flag)
wibr 172240 177000
wibr 172242 177002
wibr 172244 177004
wal 172240 -- ! verify
brm 3
d=012000
d=012002
d=012004
#
wmembe 110 -- write high byte (set sticky flag)
wibr 172240 000377
wibr 172242 022377
wibr 172244 044377
wal 172240 -- ! verify
brm 3
d=000000
d=022002
d=044004
#
wmembe 011 -- write high and low byte
wibr 172240 012340
wibr 172242 012342
wibr 172244 012344
wal 172240 -- ! verify
brm 3
d=012340
d=012342
d=012344
#
#[[off]] - this tests cp not the cpu - meaningless in simh
#
C test access error handling to memory (use 17740000)
C with wm/rm
#
wal 140000
wah 000177
.merr 1
.sdef s=01000001
wm 000000
rm d=-
.merr 0
.sdef s=00000000,01110000
#
C with bwm/brm
#
wal 140000
wah 000177
.merr 1
.sdef s=01000001
bwm 2
000000
000000
.merr 0
.sdef s=00000000,01110000
#
wal 140000
wah 000177
.merr 1
.sdef s=01000001
brm 2
d=-
d=-
.merr 0
.sdef s=00000000,01110000
#
C test access error handling to IB space (use 00160016)
C (is above ibd_ibmon decoded range, and below other debug stuff)
C with wm/rm
wal 160016
.merr 1
.sdef s=01000001
wm 000000
rm d=-
.merr 0
.sdef s=00000000,01110000
C with bwm/brm
#
wal 160016
.merr 1
.sdef s=01000001
bwm 2
000000
000000
.merr 0
.sdef s=00000000,01110000
#
wal 160016
.merr 1
.sdef s=01000001
brm 2
d=-
d=-
.merr 0
.sdef s=00000000,01110000
#[[on]]
#-----------------------------------------------------------------------------
C Setup trap catchers
#
wal 000004 -- vectors: 4...34 (trap catcher)
bwm 14
000006 -- PC:06 ; vector 4
000000 -- PS:0
000012 -- PC:12 ; vector 10
000000 -- PS:0
000016 -- PC:16 ; vector 14 (T bit; BPT)
000000 -- PS:0
000022 -- PC:22 ; vector 20 (IOT)
000000 -- PS:0
000026 -- PC:26 ; vector 24 (Power fail, not used)
000000 -- PS:0
000032 -- PC:32 ; vector 30 (EMT)
000000 -- PS:0
000036 -- PC:36 ; vector 34 (TRAP)
000000 -- PS:0
wal 000240 -- vectors: 240,244,250 (trap catcher)
bwm 6
000242 -- PC:242 ; vector 240 (PIRQ)
000000 -- PS:0
000246 -- PC:246 ; vector 244 (FPU)
000000 -- PS:0
000252 -- PC:252 ; vector 250 (MMU)
000000 -- PS:0
#
C Setup MMU
#
wal 172300 -- kernel I space DR
bwm 8
077406 -- slf=127; ed=0(up); acf=6(w/r)
077406 -- slf=127; ed=0(up); acf=6(w/r)
077406 -- slf=127; ed=0(up); acf=6(w/r)
077406 -- slf=127; ed=0(up); acf=6(w/r)
077406 -- slf=127; ed=0(up); acf=6(w/r)
077406 -- slf=127; ed=0(up); acf=6(w/r)
077406 -- slf=127; ed=0(up); acf=6(w/r)
077406 -- slf=127; ed=0(up); acf=6(w/r)
wal 172340 -- kernel I space AR
bwm 8
000000 -- 0
000200 -- 200 020000 base
000400 -- 400 040000 base
000600 -- 600 060000 base
001000 -- 1000 100000 base
001200 -- 1200 120000 base
001400 -- 1400 140000 base
177600 -- 176000 (map to I/O page)
#-----------------------------------------------------------------------------
C Setup code 1 [base 2100] (very basics: cont,start; 'simple' instructions)
#
wal 002100 -- code test 1: (sec+clc+halt)
bwm 3
000261 -- sec
000250 -- cln
000000 -- halt
#-----
wal 002120 -- code test 2: (4 *inc R2, starting from -2)
bwm 5
005202 -- inc r2
005202 -- inc r2
005202 -- inc r2
005202 -- inc r2
#2130
000000 -- halt
#-----
wal 002140 -- code test 3: (dec r3; bne -2; halt)
bwm 3
005303 -- dec r3
001376 -- bne -2
000000 -- halt
#-----
wal 002160 -- code test 4: (inc r1; sob r0,-2; halt)
bwm 3
005201 -- inc r1
077002 -- sob r0,-2
000000 -- halt
#
C Exec code 1 (very basics: start; 'simple' instructions)
C Exec test 1.1 (sec+clc+halt)
#
wpc 002100 -- pc=2100
wps 000010 -- psw: set N flag
sta -- start @ 2100
wtgo
rpc d=002106 -- ! pc
rps d=000001 -- ! N cleared, C set now
#
C Exec test 1.2 (4 *inc R2, starting from -2)
#
wr2 177776 -- r2=-2
cres
stapc 002120 -- start @ 2120
wtgo
rr2 d=000002 -- ! r2=2
rpc d=002132 -- ! pc
#
C Exec test 1.3 (dec r3; bne -2; halt)
#
wr3 000002 -- r3=2
cres
stapc 002140 -- start @ 2140
wtgo
rr3 d=000000 -- ! r3=0
rpc d=002146 -- ! pc
#
C Exec test 1.4 (inc r1; sob r0,-2; halt)
#
wr0 000002 -- r0=2
wr1 000000 -- r1=0
cres
stapc 002160 -- start @ 2160
wtgo
rr0 d=000000 -- ! r0=0
rr1 d=000002 -- ! r1=2
rpc d=002166 -- ! pc
#-----------------------------------------------------------------------------
C Setup code 2 [base 2200] (bpt against trap catcher @14)
#
wal 002200 -- code:
bwm 4
000257 -- cl(nzvc)
000261 -- sec
000003 -- bpt
000000 -- halt
#
C Exec code 2 (bpt against trap catcher @14)
#
wsp 001400 -- sp=1400
cres
stapc 002200 -- start @ 2200
wtgo
rsp d=001374 -- ! sp
rpc d=000020 -- ! pc
wal 001374
brm 2
d=002206 -- ! (sp) old pc
d=000341 -- ! 2(sp) old ps
#-----------------------------------------------------------------------------
C Setup code 3 [base 2300] (bpt against trap handler doing inc r0; rtt)
#
wal 002300 -- code:
bwm 4
000257 -- cl(nzvc)
000003 -- bpt
005201 -- inc r1
000000 -- halt
wal 000014 -- vector: 14
bwm 2
002320 -- PC:2320
000002 -- PS:2
wal 002320 -- code (trap 14):
bwm 3
005200 -- inc r0
000006 -- rtt
000000 -- halt
#
C Exec code 3 (bpt against trap handler doing inc r0; rtt)
#
wr0 000000 -- r0=0
wr1 000000 -- r1=0
wsp 001400 -- sp=1400
cres
stapc 002300 -- start @ 2300
wtgo
rr0 d=000001 -- ! r0
rr1 d=000001 -- ! r1
rsp d=001400 -- ! sp
rpc d=002310 -- ! pc
#-----------------------------------------------------------------------------
C Setup code 4 [base 2400] (enable T-trap on handler of code 3; run 2* inc r1)
#
wal 002400
bwm 4
000006 -- rtt
005201 -- inc r1
005201 -- inc r1
000000 -- halt
#
C Exec code 4 (enable T-trap on handler of code 3; run 2* inc r1)
#
wr0 000000 -- r0=0
wr1 000000 -- r1=0
wsp 001374 -- sp=1374
wal 001374 -- setup stack with rtt return frame setting T flag
bwm 2
002402 -- start address
000020 -- set T flag in PSW
cres
stapc 002400 -- start @ 2400 -> rtt -> 2402 from stack
wtgo
rr0 d=000002 -- ! r0
rr1 d=000002 -- ! r1
rsp d=001400 -- ! sp
rpc d=002410 -- ! pc
#
cres -- console reset (to clear T flag)
wal 000014 -- vector: 14 -> trap catcher again
bwm 2
000016 -- PC:16
000000 -- PS:0
#-----------------------------------------------------------------------------
C Setup code 5 [base 2500] (srcr modes: mov xxx,rn: (r0),(r0)+,-(r0),@(r0))
#
wal 002500 -- code:
bwm 6
011001 -- mov (r0),r1
012002 -- mov (r0)+,r2
012003 -- mov (r0)+,r3
014004 -- mov -(r0),r4
013005 -- mov @(r0)+,r5
000000 -- halt
#
wal 002540 -- data:
bwm 2
000070 --
002550 --
wal 002550 -- data:
bwm 2
000072 --
000074 --
#
C Exec code 5 (srcr modes: mov xxx,rn: (r0),(r0)+,-(r0),@(r0))
#
wr0 002540 -- r0=2540
wr1 000000 -- r1=0
wr2 000000 -- r2=0
wr3 000000 -- r3=0
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
cres
stapc 002500 -- start @ 2500
wtgo
rr0 d=002544 -- ! r0
rr1 d=000070 -- ! r1
rr2 d=000070 -- ! r2
rr3 d=002550 -- ! r3
rr4 d=002550 -- ! r4
rr5 d=000072 -- ! r5
rsp d=001400 -- ! sp
rpc d=002514 -- ! pc
#-----------------------------------------------------------------------------
C Setup code 6 [base 2600] (srcr modes: mov xxx,rn: x(r0),@x(r0), pc modes)
#
wal 002600 -- code:
bwm 11
016001 -- mov 2(r0),r1
000002
017002 -- mov @2(r0),r2
000002
012703 -- mov (pc)+,r3 ; #377
000377
013704 -- mov @(pc)+,r4 ; @#2552 (in previous code !)
002552
#2620
112705 -- movb (pc)+,r5 ; #377
000377
000000 -- halt
#
C Exec code 6 (srcr modes: mov xxx,rn: x(r0),@x(r0), pc modes)
#
wr0 002540 -- r0=2540 (in previous code !)
wr1 000000 -- r1=0
wr2 000000 -- r2=0
wr3 000000 -- r3=0
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
cres
stapc 002600 -- start @ 2600
wtgo
rr0 d=002540 -- ! r0
rr1 d=002550 -- ! r1
rr2 d=000072 -- ! r2
rr3 d=000377 -- ! r3
rr4 d=000074 -- ! r4
rr5 d=177777 -- ! r5
rsp d=001400 -- ! sp
rpc d=002626 -- ! pc
#-----------------------------------------------------------------------------
C Setup code 7 [base 2700] (dstw modes: mov rn,xxx: all non-r modes)
#
wal 002700 -- code:
bwm 18
012710 -- mov #110,(r0) (to 2750)
000110
012721 -- mov #120,(r1)+ (to 2752)
000120
012732 -- mov #130,@(r2)+ (to 2754)
000130
012743 -- mov #140,-(r3) (to 2756)
000140
#2720
012754 -- mov #150,@-(r4) (to 2760)
000150
012760 -- mov #160,12(r0) (to 2762)
000160
000012
012770 -- mov #170,@24(r0) (to 2764)
000170
000024
#2740
010546 -- mov r5,-(r6)
000000 -- halt
#
wal 002770 -- data:
bwm 3
002754 -- mem(2770)=2754
002760 -- mem(2772)=2760
002764 -- mem(2774)=2764
#
C Exec code 7 (dstw modes: mov rn,xxx: all non-r modes)
#
wr0 002750 -- r0=2750
wr1 002752 -- r1=2752
wr2 002770 -- r2=2770
wr3 002760 -- r3=2760
wr4 002774 -- r4=2774
wr5 000666 -- r5=666
wsp 001400 -- sp=1400
cres
stapc 002700 -- start @ 2700
wtgo
rr0 d=002750 -- ! r0
rr1 d=002754 -- ! r1
rr2 d=002772 -- ! r2
rr3 d=002756 -- ! r3
rr4 d=002772 -- ! r4
rr5 d=000666 -- ! r5
rsp d=001376 -- ! sp
rpc d=002744 -- ! pc
wal 002750
brm 7
d=000110 -- ! mem(2750)=110
d=000120 -- ! mem(2752)=120
d=000130 -- ! mem(2754)=130
d=000140 -- ! mem(2756)=140
d=000150 -- ! mem(2760)=150
d=000160 -- ! mem(2762)=160
d=000170 -- ! mem(2764)=170
wal 001376
rmi d=000666 -- ! mem(sp)=666
#-----------------------------------------------------------------------------
C Setup code 10 [base 3000] (dstm modes: inc xxx: all non-r modes)
#
wal 003000 -- code:
bwm 10
005210 -- inc (r0) (to 3050)
005221 -- inc (r1)+ (to 3052)
005232 -- inc @(r2)+ (to 3054)
005243 -- inc -(r3) (to 3056)
005254 -- inc @-(r4) (to 3060)
005260 -- inc 12(r0) (to 3062)
000012
005270 -- inc @24(r0) (to 3064)
#3020
000024
000000 -- halt
#
wal 003050 -- data:
bwm 7
000110 -- mem(3050)=110
000120 -- mem(3052)=120
000130 -- mem(3054)=130
000140 -- mem(3056)=140
000150 -- mem(3060)=150
000160 -- mem(3062)=160
000170 -- mem(3064)=170
wal 003070 -- data:
bwm 3
003054 -- mem(3070)=3054
003060 -- mem(3072)=3060
003064 -- mem(3074)=3064
#
C Exec code 10 (dstm modes: inc xxx: all non-r modes)
#
wr0 003050 -- r0=3050
wr1 003052 -- r1=3052
wr2 003070 -- r2=3070
wr3 003060 -- r3=3060
wr4 003074 -- r4=3074
wsp 001400 -- sp=1400
cres
stapc 003000 -- start @ 3000
wtgo
rr0 d=003050 -- ! r0
rr1 d=003054 -- ! r1
rr2 d=003072 -- ! r2
rr3 d=003056 -- ! r3
rr4 d=003072 -- ! r4
rpc d=003024 -- ! pc
wal 003050
brm 7
d=000111 -- ! mem(3050)=111
d=000121 -- ! mem(3052)=121
d=000131 -- ! mem(3054)=131
d=000141 -- ! mem(3056)=141
d=000151 -- ! mem(3060)=151
d=000161 -- ! mem(3062)=161
d=000171 -- ! mem(3064)=171
#-----------------------------------------------------------------------------
C Setup code 11 [base 3100; use 31-32] (dsta modes: jsr pc,xxx: all non-r modes)
#
wal 003100 -- code:
bwm 10
004710 -- jsr pc,(r0) (to 3210) r0->3210
004721 -- jsr pc,(r1)+ (to 3220) r1->3220
004732 -- jsr pc,@(r2)+ (to 3230) r2->3140->3230
004743 -- jsr pc,-(r3) (to 3240) r3->3242
004754 -- jsr pc,@-(r4) (to 3250) r4->3142->3250
004760 -- jsr pc,50(r0) (to 3260) r0->3210+50->3260
000050
004770 -- jsr pc,@-44(r0) (to 3270) r0->3210-44->3144->3270
#3120
177734
000000 -- halt
#
wal 003140 -- data:
bwm 3
003230 -- mem(3140)=3230
003250 -- mem(3142)=3250
003270 -- mem(3144)=3270
#
wal 003210 -- code:
bwm 28
012725 -- mov #110,(r5)+
000110
000207 -- rts pc
000000 -- halt
#3220
012725 -- mov #120,(r5)+
000120
000207 -- rts pc
000000 -- halt
012725 -- mov #130,(r5)+
000130
000207 -- rts pc
000000 -- halt
#3240
012725 -- mov #140,(r5)+
000140
000207 -- rts pc
000000 -- halt
012725 -- mov #150,(r5)+
000150
000207 -- rts pc
000000 -- halt
#3260
012725 -- mov #160,(r5)+
000160
000207 -- rts pc
000000 -- halt
012725 -- mov #170,(r5)+
000170
000207 -- rts pc
000000 -- halt
#
C Exec code 11 (dsta modes: jsr pc,xxx: all non-r modes)
#
wr0 003210 -- r0=3210
wr1 003220 -- r1=3220
wr2 003140 -- r2=3140
wr3 003242 -- r3=3242
wr4 003144 -- r4=3144
wr5 003160 -- r5=3160
wsp 001400 -- sp=1400
cres
stapc 003100 -- start @ 3100
wtgo
rr0 d=003210 -- ! r0=3210
rr1 d=003222 -- ! r1=3222
rr2 d=003142 -- ! r2=3142
rr3 d=003240 -- ! r3=3240
rr4 d=003142 -- ! r4=3142
rr5 d=003176 -- ! r5=3176
rsp d=001400 -- ! sp
rpc d=003124 -- ! pc
wal 003160
brm 7
d=000110 -- ! mem(3160)=110
d=000120 -- ! mem(3162)=120
d=000130 -- ! mem(3164)=130
d=000140 -- ! mem(3166)=140
d=000150 -- ! mem(3170)=150
d=000160 -- ! mem(3172)=160
d=000170 -- ! mem(3174)=170
#-----------------------------------------------------------------------------
C Setup code 12 [base 3300; use 33-34] (PSW access via sex,clx,spl,mov, and clr)
#
wal 003300 -- code:
bwm 23
011025 -- mov (r0),(r5)+
012710 -- mov #030000,(r0) ; write full PSW: pmode=um
030000
011025 -- mov (r0),(r5)+
000263 -- se(v,c)
011025 -- mov (r0),(r5)+
000237 -- spl 7
011025 -- mov (r0),(r5)+
#3320
000274 -- se(n,z)
011025 -- mov (r0),(r5)+
000233 -- spl 3
011025 -- mov (r0),(r5)+
000241 -- clc
011025 -- mov (r0),(r5)+
112710 -- movb #40,(r0) ; write PSW_low (set pri=1)
000040
#3340
011025 -- mov (r0),(r5)+
112711 -- movb #20,(r1) ; write PSW_high: pmode=sm
000020
011025 -- mov (r0),(r5)+
005010 -- clr (r0)
011025 -- mov (r0),(r5)+
000000 -- halt
#
C Exec code 12 (PSW access via sex,clx,spl,mov, and clr)
#
wps 000017 -- psw: set all condition codes (to check psw clear @ start)
#
wr0 177776 -- r0=177776
wr1 177777 -- r1=177777
wr5 003400 -- r5=3400
wsp 001400 -- sp=1400
cres
stapc 003300 -- start @ 3300
wtgo
rr5 d=003424 -- ! r5=3424
rpc d=003356 -- ! pc
wal 003400
brm 10
d=000340 -- ! mem(3400) after start
d=030000 -- ! mem(3402) after mov #030000,(r0)
d=030003 -- ! mem(3404) after se(v,c) (VC)
d=030341 -- ! mem(3406) after spl 7 (pri=7,C)
d=030355 -- ! mem(3410) after se(n,z) (pri=7,NZC)
d=030141 -- ! mem(3412) after spl 3 (pri=3,C)
d=030140 -- ! mem(3414) after clc (pri=3)
d=030040 -- ! mem(3416) after movb #40,(r0) (pri=1)
d=010040 -- ! mem(3420) after movb #20,(r1) pmode=sm
d=000000 -- ! mem(3422) after clr (r0)
#-----------------------------------------------------------------------------
C Setup code 13 [base 3500] (test WAIT and rdma (bwm/rwm while CPU running)
#
#[[off]] - can't emulate 'sto' command in simh, rdma meaningless in simh
#
wal 003500 -- code 13.1 (to be stepped)
bwm 4
000001 -- wait
000001 -- wait
000001 -- wait
000000 -- halt
#
wal 003520 -- code 13.2 (busy loop)
bwm 3
005700 -- tst r0
001776 -- beq .-1
000000 -- halt
#
wal 003540 -- code 13.3 (just a WAIT)
bwm 2
000001 -- wait
000000 -- halt
#
C Exec code 13.1a (run WAIT)
#
cres
stapc 003500 -- start @ 3500
.wait 20 -- let it go
rpc d=003502 -- ! should hang here ...
.wait 20 -- let it go
rpc d=003502 -- ! should hang here ...
.sdef s=00001000
sto
.sdef s=00000000,01110000
wtlam d=000001 -- harvest attn due to go 1->0 transition of sto command
rpc d=003502 -- ! should stay there ...
#
C Exec code 13.1b (step WAIT)
wpc 003500 -- pc=3500
step -- step over 1st WAIT
rpc d=003502 -- !
step -- step over 2nd WAIT
rpc d=003504 -- !
step -- step over 3rd WAIT
rpc d=003506 -- !
step -- step over HALT
rpc d=003510 -- !
#
C Exec code 13.2 (test bwm/brm while CPU busy looping)
wr0 000000 -- r0=0
cres
stapc 003520 -- start @ 3520
#
wal 003560 -- write data while CPU active
bwm 8
003560
003562
003564
003566
003570
003572
003574
003576
wal 003560 -- read data while CPU active
brm 8
d=003560
d=003562
d=003564
d=003566
d=003570
d=003572
d=003574
d=003576
#
wr0 000001 -- r0=1 --> should end loop
wtgo
rpc d=003526 -- !
#
C Exec code 13.3 (test bwm/brm while CPU on WAIT)
#
cres
stapc 003540 -- start @ 3540
#
wal 003560 -- write data while CPU active
bwm 8
073560
073562
073564
073566
073570
073572
073574
073576
wal 003560 -- read data while CPU active
brm 8
d=073560
d=073562
d=073564
d=073566
d=073570
d=073572
d=073574
d=073576
#
.sdef s=00001000
sto
.sdef s=00000000,01110000
wtlam d=000001 -- harvest attn due to go 1->0 transition of sto command
rpc d=003542 -- !
#[[on]]
#-----------------------------------------------------------------------------
# Setup code 14 --- code 14 doesn't exist anymore...
#-----------------------------------------------------------------------------
C Setup code 15 [base 3600; use 36-37] (test 4 traps)
#
wal 003600 -- code:
bwm 5
000003 -- bpt (to 14)
000004 -- iot (to 20)
104077 -- emt 77 (to 30)
104477 -- trap 77 (to 34)
000000 -- halt
#
wal 003620 -- code: trap handlers
bwm 11
010025 -- mov r0,(r5)+ (@ 3620)
000405 -- br .+10
010125 -- mov r1,(r5)+ (@ 3624)
000403 -- br .+6
010225 -- mov r2,(r5)+ (@ 3630)
000401 -- br .+2
010325 -- mov r3,(r5)+ (@ 3634)
#3640
011604 -- mov (sp),r4 ; r4 points after instruction
016425 -- mov -2(r4),(r5)+ ; load instruction
177776
000002 -- rti
#
wal 000014 -- vector: 14+20
bwm 4
003620 -- PC:3620
000000 -- PS:0
003624 -- PC:3624
000000 -- PS:0
wal 000030 -- vector: 30+34
bwm 4
003630 -- PC:3630
000000 -- PS:0
003634 -- PC:3634
000000 -- PS:0
#
C Exec code 15 (test 4 traps)
#
wr0 000011 -- r0=11
wr1 000022 -- r1=22
wr2 000033 -- r2=33
wr3 000044 -- r3=44
wr5 003700 -- r5=3700
wsp 001400 -- sp=140
cres
stapc 003600 -- start @ 3600
wtgo
rr5 d=003720 -- ! r5=3720
rsp d=001400 -- ! sp
rpc d=003612 -- ! pc
wal 003700
brm 8
d=000011 -- ! mem(3700)=11
d=000003 -- ! mem(3702)=3
d=000022 -- ! mem(3704)=22
d=000004 -- ! mem(3706)=4
d=000033 -- ! mem(3710)=33
d=104077 -- ! mem(3712)=104077
d=000044 -- ! mem(3714)=44
d=104477 -- ! mem(3716)=104477
wal 000014 -- vector: 14+20 -> trap catcher again
bwm 4
000016 -- PC:16
000000 -- PS:0
000022 -- PC:22
000000 -- PS:0
wal 000030 -- vector: 30+34 -> trap catcher again
bwm 4
000032 -- PC:32
000000 -- PS:0
000036 -- PC:36
000000 -- PS:0
#-----------------------------------------------------------------------------
C Setup code 16 [base 4000] (enable MMU, check ssr1, ssr2 response)
#
wal 172516 -- SSR3
wmi 000002 -- I/D enabled for sm only (to check CRESET)
wal 177572 -- SSR0
wmi 000001 -- set enable bit
#
wal 004000 -- code (to be single stepped...)
bwm 7
011105 -- mov (r1),r5
012105 -- mov (r1)+,r5
014105 -- mov -(r1),r5
012122 -- mov (r1)+,(r2)+
112105 -- movb (r1)+,r5
112721 -- movb #200,(r1)+
000200
#
wal 004030 -- code test 1:
wmi 000000 -- halt
#
wal 004040 -- data:
bwm 2
000001
000300
#
C Exec code 16 (enable MMU, check ssr1, ssr2 response)
#
wr1 004040 -- r1=4040
wr2 004060 -- r2=4060
wsp 001400 -- sp=1400
wpc 004000 -- pc=4000
step -- step (mov (r1),r5)
wal 177572 -- check SSR0/1/2
brm 3
d=000001 -- ! SSR0: (ena=1)
d=000000 -- ! SSR1:
d=004000 -- ! SSR2: 4000 (eff. PC)
rr1 d=004040 -- ! r1
rr5 d=000001 -- ! r5
step -- step (mov (r1)+,r5)
wal 177572 -- check SSR0/1/2
brm 3
d=000001 -- ! SSR0: (ena=1)
d=000021 -- ! SSR1: rb none; ra=1,+2
d=004002 -- ! SSR2: 4002 (eff. PC)
rr1 d=004042 -- ! r1
rr5 d=000001 -- ! r5
step -- step (mov -(r1),r5)
wal 177572 -- check SSR0/1/2
brm 3
d=000001 -- ! SSR0: (ena=1)
d=000361 -- ! SSR1: rb none; ra=1,-2
d=004004 -- ! SSR2: 4004 (eff. PC)
rr1 d=004040 -- ! r1
rr5 d=000001 -- ! r5
step -- step (mov (r1)+,(r2)+)
wal 177572 -- check SSR0/1/2
brm 3
d=000001 -- ! SSR0: (ena=1)
d=011021 -- ! SSR1: rb=2,2; ra=1,2
d=004006 -- ! SSR2: 4006 (eff. PC)
rr1 d=004042 -- ! r1
rr2 d=004062 -- ! r2
step -- step (movb (r1)+,r5)
wal 177572 -- check SSR0/1/2
brm 3
d=000001 -- ! SSR0: (ena=1)
d=000011 -- ! SSR1: rb=none; ra=1,1
d=004010 -- ! SSR2: 4010 (eff. PC)
rr1 d=004043 -- ! r1
rr5 d=177700 -- ! r5
step -- step (movb #200,(r1)+)
wal 177572 -- check SSR0/1/2
brm 3
d=000001 -- ! SSR0: (ena=1)
d=004427 -- ! SSR1: rb=1,1; ra=7,2
d=004012 -- ! SSR2: 4012 (eff. PC)
rr1 d=004044 -- ! r1
#
C Exec test 16.1 (check CRESET of PSW, SSR0, SSR3 after start)
#
wps 000000 -- psw: set pri=0
cres
stapc 004030 -- start @ 4030 (just HALT, testing console reset)
wtgo
rpc d=004032 -- ! pc=4032
rps d=000340 -- ! psw: reset by CRESET
wal 172516 -- SSR3
rmi d=000000 -- ! cleared by CRESET
wal 177572 -- SSR0
rmi d=000000 -- ! cleared by CRESET
#-----------------------------------------------------------------------------
C Setup code 17 [base 4100; use 41-46] (basic instruction and cc test)
#
wal 004100 -- code: (length 70)
bwm 32
010124 -- mov r1,(r4)+ (#4711, #123456)
020124 -- cmp r1,(r4)+ (#4711, #123456)
020224 -- cmp r2,(r4)+ (#123456,#4711)
020124 -- cmp r1,(r4)+ (#4711, #4711)
005024 -- clr (r4)+ (#123456)
030124 -- bit r1,(r4)+ (#4711, #11)
030124 -- bit r1,(r4)+ (#4711, #66)
040124 -- bic r1,(r4)+ (#4711, #123456)
#4120
050124 -- bis r1,(r4)+ (#4711, #123456)
060124 -- add r1,(r4)+ (#4711, #123456)
160124 -- sub r1,(r4)+ (#4711, #123456)
005124 -- com (r4)+ (#123456)
005224 -- inc (r4)+ (#123456)
005324 -- dec (r4)+ (#123456)
005424 -- neg (r4)+ (#123456)
005724 -- tst (r4)+ (#123456)
#4140
006024 -- ror (r4)+ (#100201) Cin=0; Cout=1
006024 -- ror (r4)+ (#002201) Cin=1; Cout=1
006124 -- rol (r4)+ (#100200) Cin=1; Cout=1
006224 -- asr (r4)+ (#200)
006224 -- asr (r4)+ (#100200)
006324 -- asl (r4)+ (#200)
006324 -- asl (r4)+ (#100200)
060124 -- add r1,(r4)+ (#4711, #077777)
#4160
005524 -- adc (r4)+ (#200)
160124 -- sub r1,(r4)+ (#4711, #4700)
005624 -- sbc (r4)+ (#200)
000324 -- swap (r4)+ (#111000)
006724 -- sxt (r4)+ (#111111 with N=1)
074124 -- xor r1,(r4)+ (#070707,#4711)
006724 -- sxt (r4)+ (#111111 with N=0)
000000 -- halt
#
wal 000014 -- vector: 14
bwm 2
004270 -- PC:4270
000000 -- PS:0
#-----
wal 004270 -- code: (trap 14):
bwm 3
016625 -- mov 2(sp),(r5)+
000002
000006 -- rtt
#-----
wal 004300 -- data 1: (length 66)
bwm 31
123456 --
123456 --
004711 --
004711 --
123456 --
000011 --
000066 --
123456 --
#4320
123456 --
123456 --
123456 --
123456 --
123456 --
123456 --
123456 --
123456 --
#4340
100201 --
002201 --
100200 --
000200 --
100200 --
000200 --
100200 --
177000 --
#4360
000200 --
004701 --
000200 --
111000 --
111111 --
070707 --
111111 --
#
C Exec code 17 (basic instruction and cc test)
#
wr1 004711 -- r1=4711
wr2 123456 -- r2=123456
wr4 004300 -- r4=4300
wr5 004500 -- r5=4500
wsp 001374 -- sp=1374
wal 001374 -- setup stack with rtt return frame setting T flag
bwm 2
004100 -- start address (code 17 @ 4100)
000020 -- set T flag in PSW
cres
stapc 004274 -- start @ 4274 -> rtt -> 4100 from stack
wtgo
rr1 d=004711 -- ! r1=4711
rr2 d=123456 -- ! r2=123456
rr4 d=004376 -- ! r4=4376
rr5 d=004576 -- ! r5=4576
rsp d=001400 -- ! sp=1400
rpc d=004200 -- ! pc=4200
wal 004300
brm 31
d=004711 -- ! mem(4300)=004711; mov r1,(r4)+ (#4711, #123456)
d=123456 -- ! mem(4302)=123456; cmp r1,(r4)+ (#4711, #123456)
d=004711 -- ! mem(4304)=004711; cmp r1,(r4)+ (#123456,#4711)
d=004711 -- ! mem(4306)=004711; cmp r1,(r4)+ (#4711, #4711)
d=000000 -- ! mem(4310)=000000; clr (r4)+ (#123456)
d=000011 -- ! mem(4312)=000011; bit r1,(r4)+ (#4711, #11)
d=000066 -- ! mem(4314)=000066; bit r1,(r4)+ (#4711, #66)
d=123046 -- ! mem(4316)=123046; bic r1,(r4)+ (#4711, #123456)
d=127757 -- ! mem(4320)=127757; bis r1,(r4)+ (#4711, #123456)
d=130367 -- ! mem(4322)=130367; add r1,(r4)+ (#4711, #123456)
d=116545 -- ! mem(4324)=116545; sub r1,(r4)+ (#4711, #123456)
d=054321 -- ! mem(4326)=054321; com (r4)+ (#123456)
d=123457 -- ! mem(4330)=123457; inc (r4)+ (#123456)
d=123455 -- ! mem(4332)=123455; dec (r4)+ (#123456)
d=054322 -- ! mem(4334)=054322; neg (r4)+ (#123456)
d=123456 -- ! mem(4336)=123456; tst (r4)+ (#123456)
d=040100 -- ! mem(4340)=040100; ror (r4)+ (#100201)
d=101100 -- ! mem(4342)=101100; ror (r4)+ (#002201)
d=000401 -- ! mem(4344)=000401; rol (r4)+ (#100200)
d=000100 -- ! mem(4346)=000100; asr (r4)+ (#200)
d=140100 -- ! mem(4350)=140100; asr (r4)+ (#100200)
d=000400 -- ! mem(4352)=000400; asl (r4)+ (#200)
d=000400 -- ! mem(4354)=000400; asl (r4)+ (#100200)
d=003711 -- ! mem(4356)=003711; add r1,(r4)+ (#4711, ,#177000)
d=000201 -- ! mem(4360)=000201; adc (r4)+ (#200)
d=177770 -- ! mem(4362)=177770; sub r1,(r4)+ (#4711, #4701)
d=000177 -- ! mem(4364)=000177; sbc (r4)+ (#200)
d=000222 -- ! mem(4366)=000222; swap (r4)+ (#111000)
d=177777 -- ! mem(4370)=177777; sxt (r4)+ (#111111)
d=074016 -- ! mem(4372)=074016; xor r1,(r4)+ (#070707)
d=000000 -- ! mem(4374)=000000; sxt (r4)+ (#111111)
#
wal 004500 -- NZVC
brm 31
d=000020 -- ! mem(4500)=0000; mov r1,(r4)+ (#4711, #123456)
d=000021 -- ! mem(4502)=000C; cmp r1,(r4)+ (#4711, #123456)
d=000030 -- ! mem(4504)=N000; cmp r1,(r4)+ (#123456,#4711)
d=000024 -- ! mem(4506)=0Z00; cmp r1,(r4)+ (#4711, #4711)
d=000024 -- ! mem(4510)=0Z00; clr (r4)+ (#123456)
d=000020 -- ! mem(4512)=0000; bit r1,(r4)+ (#4711, #11)
d=000024 -- ! mem(4514)=0Z00; bit r1,(r4)+ (#4711, #66)
d=000030 -- ! mem(4516)=N000; bic r1,(r4)+ (#4711, #123456)
d=000030 -- ! mem(4520)=N000; bis r1,(r4)+ (#4711, #123456)
d=000030 -- ! mem(4522)=N000; add r1,(r4)+ (#4711, #123456)
d=000030 -- ! mem(4524)=N000; sub r1,(r4)+ (#4711, #123456)
d=000021 -- ! mem(4526)=000C; com (r4)+ (#123456)
d=000031 -- ! mem(4530)=N00C; inc (r4)+ (#123456) keep C!
d=000031 -- ! mem(4532)=N00C; dec (r4)+ (#123456) keep C!
d=000021 -- ! mem(4534)=000C; neg (r4)+ (#123456)
d=000030 -- ! mem(4536)=N000; tst (r4)+ (#123456)
d=000023 -- ! mem(4540)=00VC; ror (r4)+ (#100201)
d=000031 -- ! mem(4542)=N00C; ror (r4)+ (#002201)
d=000023 -- ! mem(4544)=00VC; rol (r4)+ (#100200)
d=000020 -- ! mem(4546)=0000; asr (r4)+ (#200)
d=000032 -- ! mem(4550)=N0V0; asr (r4)+ (#100200)
d=000020 -- ! mem(4552)=0000; asl (r4)+ (#200)
d=000023 -- ! mem(4554)=00VC; asl (r4)+ (#100200)
d=000021 -- ! mem(4556)=000C; add r1,(r4)+ (#4711, ,#177000)
d=000020 -- ! mem(4560)=0000; adc (r4)+ (#200)
d=000031 -- ! mem(4562)=N00C; sub r1,(r4)+ (#4711, #4701)
d=000020 -- ! mem(4564)=0000; sbc (r4)+ (#200)
d=000030 -- ! mem(4566)=N000; swap (r4)+ (#111000)
d=000030 -- ! mem(4570)=N000; sxt (r4)+ (#111111 with N=1)
d=000020 -- ! mem(4572)=0000; xor r1,(r4)+ (#4711, #070707)
d=000024 -- ! mem(4574)=0Z00; sxt (r4)+ (#111111 with N=0)
#
cres -- console reset (to clear T flag)
wal 000014 -- vector: 14 -> trap catcher again
bwm 2
000016 -- PC:16
000000 -- PS:0
#-----------------------------------------------------------------------------
C Setup code 20 [base 4700] (check CPUERR and error handling)
#[[off]]
wal 004700 -- code (to be single stepped...)
bwm 11
010025 -- mov r0,(r5)+ (@ 4777)
010025 -- mov r0,(r5)+ (@ 150000)
010025 -- mov r0,(r5)+ (@ 160000)
000101 -- jmp r1
004701 -- jsr pc,r1
000000 -- halt
014321 -- mov -(r3),(r1)+ (@ 20000)
024321 -- cmp -(r3),(r1)+ (@ 20400)
#4720
064321 -- add -(r3),(r1)+ (@ 20000)
010046 -- mov r0,-(sp) (@ 340)
000004 -- iot (with sp=342,...)
#
wal 000004 -- vector: 4+10 (trap catch)
bwm 4
000006 -- PC:6
000000 -- PS:0
000012 -- PC:12
000000 -- PS:0
#----------
C Exec code 20 (check CPUERR and error handling)
C Exec test 20.1 (odd address abort)
cres -- console reset
wps 000000 -- psw: clear
wal 001374 -- clean stack
bwm 2
000000 --
000000 --
wal 177766 -- check initial CPUERR (=0!)
rm d=000000 -- !
wr0 000011 -- r0=11
wr5 004775 -- r5=4775
wsp 001400 -- sp=1400
wpc 004700 -- pc=4700
step -- step (mov r0,(r5)+): trap 4 + CPUERR.adderr set [[s:2]]
rpc d=000006 -- ! pc=6 (trap 4 catch)
rsp d=001374 -- ! sp=1374
wal 001374 -- check stack
brm 2
d=004702 -- ! pc=4702
d=000000 -- ! ps=0
wal 177766 -- check CPUERR
rm d=000100 -- ! CPUERR: (adderr=1)
wm 000000 -- any write access will clear CPUERR
rm d=000000 -- ! CPUERR: 0
#----------
C Exec test 20.2 (non-existent memory abort)
wal 172354 -- kernel I space AR(6)
wm 177400 -- (map to 8 k below I/O page, never available in w11a)
wal 177572 -- SSR0
wmi 000001 -- enable
wal 172516 -- SSR3
wmi 000020 -- ena_22bit=1
#
wr5 140000 -- r5=140000
wsp 001400 -- sp=1400
wpc 004702 -- pc=4702
step -- step (mov r0,(r5)+): trap 4 + CPUERR.nxm set [[s:2]]
rpc d=000006 -- ! pc= 6 (trap 4 catch)
rsp d=001374 -- ! sp=1374
wal 177766 -- check CPUERR
rm d=000040 -- ! CPUERR: (nxm=1)
wm 000000 -- any write access will clear CPUERR
rm d=000000 -- ! CPUERR: 0
#
wal 177572 -- SSR0
wmi 000000 -- disable
wal 172354 -- kernel I space AR(6)
wm 001400 -- 1400 140000 base (default 1-to-1 map)
#----------
C Exec test 20.3 (I/O bus timeout abort)
wr5 160000 -- r5=160000
wsp 001400 -- sp=1400
wpc 004704 -- pc=4704
step -- step (mov r0,(r5)+): trap 4 + CPUERR.iobto set [[s:2]]
rpc d=000006 -- ! pc= 6 (trap 4 catch)
rsp d=001374 -- ! sp=1374
wal 177766 -- check CPUERR
rm d=000020 -- ! CPUERR: (iobto=1)
wm 000000 -- clear CPUERR
#----------
C Exec test 20.4 (address error abort after jmp r1)
wsp 001400 -- sp=1400
wpc 004706 -- pc=4706
step -- step (jmp r1): trap 10 [[s:2]]
rpc d=000012 -- ! pc=12 (trap 10 catch)
rsp d=001374 -- ! sp=1374
wal 177766 -- check CPUERR
rm d=000000 -- ! CPUERR: none
wm 000000 -- clear CPUERR
#----------
C Exec test 20.5 (address error abort after jsr pc,r1)
wsp 001400 -- sp=1400
wpc 004710 -- pc=4710
step -- step (jsr pc,r1): trap 10 [[s:2]]
rpc d=000012 -- ! pc=12 (trap 10 catch)
rsp d=001374 -- ! sp=1374
wal 177766 -- check CPUERR
rm d=000000 -- ! CPUERR: none
wm 000000 -- clear CPUERR
#----------
C Exec test 20.6 (halt in user mode)
wsp 001400 -- sp=1400 (kernel)
wpc 004712 -- pc=4712
wps 170000 -- psw: cmode=pmode=11 (user)
step -- step (halt): trap 4 + CPUERR.illhlt set [[s:2]]
rpc d=000006 -- ! pc=6 (trap 4 catch)
rsp d=001374 -- ! sp=1374 (now kernel again...)
wal 001374 -- check stack
brm 2
d=004714 -- !
d=170000 -- !
wal 177766 -- check CPUERR
rm d=000200 -- ! CPUERR: (illhlt=1)
wm 000000 -- clear CPUERR
#
wps 000000 -- psw: cmode=pmode=0 (kernel)
#----------
#
# test mmu aborts
#
wal 000250 -- vector: 250 -> trap catcher
bwm 2
000252 -- PC:252
000000 -- PS:0
#
wal 177572 -- SSR0
wmi 000001 -- enable
wal 172302 -- kernel I space DR segment 1 (base 20000)
wmi 077400 -- slf=127; ed=0(up); acf=0 (non-resident)
#----------
C Exec test 20.7 (non resident abort)
wr1 020000 -- r1=20000
wr3 000016 -- r3=16 ; the -(r3) fetches the mem(14)=16
wsp 001400 -- sp=1400
wpc 004714 -- pc=4714
step -- step (mov -(r3),(r1)+): abort to 250 [[s:2]]
rr1 d=020002 -- ! r1=20002 (inc done before trap (here dstw))
rr3 d=000014 -- ! r3=16 (dec done before trap)
rpc d=000252 -- ! pc=252 (trap 250 catch)
rsp d=001374 -- ! sp=1374
wal 177572 -- check SSR0/1/2
brm 3
d=100003 -- ! SSR0: (abo_nonres=1,seg=1,ena=1)
d=010763 -- ! SSR1: rb=1,2; ra=3,-2
d=004714 -- ! SSR2: 4714 (eff. PC)
#
wal 177572 -- SSR0
wmi 000001 -- enable and clear error bits
#----------
C Exec test 20.8 (segment length violation abort)
wal 172302 -- kernel I space DR segment 1 (base 20000)
wmi 001406 -- slf=3; ed=0(up); acf=6 (w/r)
#
wr1 020400 -- r1=20400
wr3 000016 -- r3=16 ; the -(r3) fetches the mem(14)=16
wsp 001400 -- sp=1400
wpc 004716 -- pc=4716
step -- step (cmp -(r3),(r1)+): abort to 250 [[s:2]]
rr1 d=020402 -- ! r1=20402 (inc done before trap (here dstr))
rr3 d=000014 -- ! r3=16 (dec done before trap)
rpc d=000252 -- ! pc=252 (trap 250 catch)
rsp d=001374 -- ! sp=1374
wal 177572 -- check SSR0/1/2
brm 3
d=040003 -- ! SSR0: (abo_length=1,seg=1,ena=1)
d=010763 -- ! SSR1: rb=1,2; ra=3,-2
d=004716 -- ! SSR2: 4716 (eff. PC)
#
wal 177572 -- SSR0
wmi 000001 -- enable and clear error bits
#----------
C Exec test 20.9 (read-only abort)
wal 172302 -- kernel I space DR segment 1 (base 20000)
wmi 077402 -- slf=127; ed=0(up); acf=2 (read-only)
#
wr1 020000 -- r1=20000
wr3 000016 -- r3=16 ; the -(r3) fetches the mem(14)=16
wsp 001400 -- sp=1400
wpc 004720 -- pc=4720
step -- step (add -(r3),(r1)+): abort to 250 [[s:2]]
rr1 d=020002 -- ! r1=20000 (inc done before trap (here dstm))
rr3 d=000014 -- ! r3=16 (dec done before trap)
rpc d=000252 -- ! pc=252 (trap 250 catch)
rsp d=001374 -- ! sp=1374
wal 177572 -- check SSR0/1/2
brm 3
d=020003 -- ! SSR0: (abo_rdonly=1,seg=1,ena=1)
d=010763 -- ! SSR1: rb=1,2; ra=3,-2
d=004720 -- ! SSR2: 4720 (eff. PC)
#
# mmu back to default setup, disable
wal 172302 -- kernel I space DR segment 1 (base 20000)
wmi 077406 -- slf=127; ed=0(up); acf=6 (r/w)
wal 177572 -- SSR0
wmi 000000 -- disable
#----------
#
# test mmu trap
#
wal 177572 -- SSR0
wmi 001001 -- enable, trap enable
wal 172302 -- kernel I space DR segment 1 (base 20000)
wmi 077404 -- slf=127; ed=0(up); acf=4 (r/w, trap on r/w)
#----------
C Exec test 20.10 (trap on write)
wr1 020000 -- r1=20000
wr3 000016 -- r3=16 ; the -(r3) fetches the mem(14)=16
wsp 001400 -- sp=1400
wpc 004714 -- pc=4714
step -- step (mov -(r3),(r1)+): trap to 250 [[s:2]]
rr1 d=020002 -- ! r1=20002 (inc done before trap)
rr3 d=000014 -- ! r3=16 (dec done before trap)
rpc d=000252 -- ! pc=252 (trap 250 catch)
rsp d=001374 -- ! sp=1374
wal 020000 -- check target area
rm d=000016 -- ! mem(20000)=16
wm 000000 -- clean tainted memory
wal 177572 -- check SSR0
brm 3
d=011001 -- ! SSR0: (trap_mmu=1,ena_trap=1,seg=0,ena=1)
d=010763 -- ! SSR1: rb=1,2; ra=3,-2
d=004714 -- ! SSR2: 4714 (eff. PC)
#----------
C Exec test 20.11 (2nd write, should not trap again)
wr1 020002 -- r1=20002
wr3 000016 -- r3=16 ; the -(r3) fetches the mem(14)=16
wsp 001400 -- sp=1400
wpc 004714 -- pc=4714
step -- step (mov -(r3),(r1)+): no trap [[s:2]]
rr1 d=020004 -- ! r1=20004 (inc done before trap)
rr3 d=000014 -- ! r3=16 (dec done before trap)
rpc d=004716 -- ! pc=252 (trap 250 catch)
rsp d=001400 -- ! sp=1374
wal 020002 -- check target area
rm d=000016 -- ! mem(20002)=16
wm 000000 -- clean tainted memory
wal 177572 -- check SSR0
brm 3
d=011003 -- ! SSR0: (trap_mmu=1,ena_trap=1,seg=1,ena=1)
d=010763 -- ! SSR1: rb=1,2; ra=3,-2
d=004714 -- ! SSR2: 4714 (eff. PC)
#
# mmu back to default setup, disable
wal 172302 -- kernel I space DR segment 1 (base 20000)
wmi 077406 -- slf=127; ed=0(up); acf=6 (r/w)
wal 177572 -- SSR0
wmi 000000 -- disable
#----------
#
# now test stack limit logic
#
C Exec test 20.12 (red stack abort when pushing data to stack)
wr0 123456 -- r0=123456
wsp 000340 -- sp=340
wpc 004722 -- pc=4722
step -- step (mov r0,-(sp)): abort to 4 [[s:2]]
rpc d=000006 -- ! pc=6 (trap 4 catch)
rsp d=000000 -- ! sp=0
wal 000336 -- check that stack wasn't written
rm d=000000 -- ! mem(336) untainted
wal 000000 -- check emergency stack at 0,2
brm 2
d=004724 -- ! mem(0): PC
d=000010 -- ! mem(2): PS
wal 177766 -- check CPUERR
rm d=000004 -- ! CPUERR: (rsv=1)
wm 000000 -- clear CPUERR
#----------
C Exec test 20.13 (red stack abort on 2nd word of interrupt/trap push)
#wps 000017 -- psw: set all cc flags
#wsp 000342 -- sp=342
#wpc 004724 -- pc=4724
#step -- step (iot): abort to 4 [[s:2]]
#rpc d=000006 -- ! pc=6 (trap 4 catch)
#rsp d=000000 -- ! sp=0
#wal 000336 -- check stack
#brm 2
# d=000000 -- ! mem(336) untainted
# d=000017 -- ! mem(340) PS of 1st attempt
#wal 000000 -- check emergency stack at 0,2
#brm 2
# d=004726 -- ! mem(0): PC
# d=000000 -- ! mem(2): PS (will be 0, orgininal PS lost !!)
#wal 177766 -- check CPUERR
#rm d=000004 -- ! CPUERR: (rsv=1)
#wm 000000 -- clear CPUERR
#----------
C Exec test 20.14 (yellow stack trap when pushing data to stack; sp=400)
wps 000017 -- psw: set all cc flags
wr0 123456 -- r0=123456
wsp 000400 -- sp=400
wpc 004722 -- pc=4722
step -- step (mov r0,-(sp)): trap to 4
rpc d=000006 -- ! pc=6 (trap 4 catch)
rsp d=000372 -- ! sp=372
wal 000372 -- check stack
brm 3
d=004724 -- ! mem(372) PC of trapped instruction
d=000011 -- ! mem(374) PS of trapped instruction
d=123456 -- ! mem(376) pushed word
wal 177766 -- check CPUERR
rm d=000010 -- ! CPUERR: (ysv=1)
wm 000000 -- clear CPUERR
#----------
C Exec test 20.15 (yellow stack trap on 2nd word of interrupt/trap push; sp=402)
wps 000017 -- psw: set all cc flags
wsp 000402 -- sp=402
wpc 004724 -- pc=4724
step -- step (iot): abort to 4 [[s:2]]
rpc d=000006 -- ! pc=6 (trap 4 catch)
rsp d=000372 -- ! sp=372
wal 000372 -- check stack
brm 4
d=000022 -- ! mem(372) PC of IOT handler
d=000000 -- ! mem(374) PS of IOT handler
d=004726 -- ! mem(376) PC of IOT trap
d=000017 -- ! mem(400) PS of IOT trap
wal 177766 -- check CPUERR
rm d=000010 -- ! CPUERR: (ysv=1)
wm 000000 -- clear CPUERR
#----------
# now test red stack escalation
#
C Exec test 20.16 (red stack escalation: abort kernel stack odd; sp=1001)
wr0 123456 -- r0=123456
wsp 001001 -- sp=1001
wpc 004722 -- pc=4722
step -- step (mov r0,-(sp)): abort to 4 [[s:2]]
rpc d=000006 -- ! pc=6 (trap 4 catch)
rsp d=000000 -- ! sp=0
wal 000000 -- check emergency stack at 0,2
brm 2
d=004724 -- ! mem(0): PC
d=000010 -- ! mem(2): PS
wal 177766 -- check CPUERR
rm d=000104 -- ! CPUERR: (rsv=1,adderr=1)
wm 000000 -- clear CPUERR
#----------
C Exec test 20.17 (red stack escalation: abort kernel stack in non-mem)
wal 172354 -- kernel I space AR(6)
wm 177400 -- (map to 8 k below I/O page, never available in w11a)
wal 177572 -- SSR0
wmi 000001 -- enable
wal 172516 -- SSR3
wmi 000020 -- ena_22bit=1
#
wr0 123456 -- r0=123456
wsp 140004 -- sp=140004
wpc 004722 -- pc=4722
step -- step (mov r0,-(sp)): abort to 4 [[s:2]]
rpc d=000006 -- ! pc=6 (trap 4 catch)
rsp d=000000 -- ! sp=0
wal 000000 -- check emergency stack at 0,2
brm 2
d=004724 -- ! mem(0): PC
d=000010 -- ! mem(2): PS
wal 177766 -- check CPUERR
rm d=000044 -- ! CPUERR: (rsv=1,nxm=1)
wm 000000 -- clear CPUERR
#
wal 177572 -- SSR0
wmi 000000 -- disable
wal 172354 -- kernel I space AR(6)
wm 001400 -- 1400 140000 base (default 1-to-1 map)
#----------
C Exec test 20.18 (red stack escalation: abort kernel stack iob-to;sp=160004)
wr0 123456 -- r0=123456
wsp 160004 -- sp=160004
wpc 004722 -- pc=4722
step -- step (mov r0,-(sp)): abort to 4 [[s:2]]
rpc d=000006 -- ! pc=6 (trap 4 catch)
rsp d=000000 -- ! sp=0
wal 000000 -- check emergency stack at 0,2
brm 2
d=004724 -- ! mem(0): PC
d=000010 -- ! mem(2): PS
wal 177766 -- check CPUERR
rm d=000024 -- ! CPUERR: (rsv=1,iobto=1)
wm 000000 -- clear CPUERR
#----------
C Exec test 20.19 (red stack escalation: abort kernel stack mmu abort;sp=020004)
#
wal 177572 -- SSR0
wmi 000001 -- enable
wal 172302 -- kernel I space DR segment 1 (base 20000)
wmi 077400 -- slf=127; ed=0(up); acf=0 (non-resident)
#
wr0 123456 -- r0=123456
wsp 020004 -- sp=020004
wpc 004722 -- pc=4722
step -- step (mov r0,-(sp)): abort to 4 [[s:2]]
rpc d=000006 -- ! pc=6 (trap 4 catch)
rsp d=000000 -- ! sp=0
wal 020002 -- check that stack wasn't written
rm d=000000 -- ! mem(20002) untainted
wal 000000 -- check emergency stack at 0,2
brm 2
d=004724 -- ! mem(0): PC
d=000010 -- ! mem(2): PS
wal 177766 -- check CPUERR
rm d=000104 -- ! CPUERR: (rsv=1,adderr=1)
wm 000000 -- clear CPUERR
# mmu back to default setup
wal 172302 -- kernel I space DR segment 1 (base 20000)
wmi 077406 -- slf=127; ed=0(up); acf=6 (r/w)
wal 177572 -- SSR0
wmi 000000 -- disable
wal 172516 -- SSR3
wmi 000000 -- disable
#
#[[on]]
#-----------------------------------------------------------------------------
C Setup code 21 [base 4740] (MTPx/MFPx; MMU for user mode with I/D)
#
#use setting as for test 22
wal 177600 -- user I space DR
wmi 077406 -- slf=127; ed=0(up); acf=6(w/r)
wal 177620 -- user D space DR
wmi 077406 -- slf=127; ed=0(up); acf=6(w/r)
wal 177640 -- user I space AR
wmi 000053 -- 53 -> maps 0 -> 5300
wal 177660 -- user D space AR
wmi 000055 -- 55 -> maps 0 -> 5500
wal 177572 -- SSR0
wmi 000001 -- set enable bit
wal 172516 -- SSR3
wmi 000001 -- enable D space for user mode
#
wal 004740 -- code (to be single stepped...)
bwm 6
006610 -- mtpi (r0)
106610 -- mtpd (r0)
006606 -- mtpi r6
006510 -- mfpi (r0)
106510 -- mfpd (r0)
006506 -- mfpi r6
#
C Exec code 21 (MTPx/MFPx; MMU for user mode with I/D)
#
wps 030000 -- psw: cmode=0, pmode=11
wal 001372 -- setup kernel stack
bwm 3
012300 --
001230 --
000666 --
wr0 000002 -- r0=2
wsp 001372 -- sp=1372
#
wpc 004740 -- pc=4740
step -- step (mtpi (r0))
rpc d=004742 -- ! pc=next
rsp d=001374 -- ! sp=1374 (one popped)
wal 005302 -- user I base
rm d=012300 -- ! mem_ui(2) = 012300
#
step -- step (mtpd (r0))
rpc d=004744 -- ! pc=next
rsp d=001376 -- ! sp=1376 (one popped)
wal 005502 -- user D base
rm d=001230 -- ! mem_ud(2) = 001230
#
step -- step (mtpi r6)
rpc d=004746 -- ! pc=next
rsp d=001400 -- ! sp=1400 (one popped)
wps 170000 -- psw: cmode=11, pmode=11
rsp d=000666 -- ! sp_um=666 [[usp]]
wps 030000 -- psw: cmode=0, pmode=11
#
wal 001374 -- clear stack
bwm 3
000000 --
000000 --
000000 --
#
step -- step (mfpi (r0))
rpc d=004750 -- ! pc=next
rsp d=001376 -- ! sp=1376 (one pushed)
wal 001376 -- top of stack
rm d=012300 -- !
#
step -- step (mfpd (r0))
rpc d=004752 -- ! pc=next
rsp d=001374 -- ! sp=1374 (one pushed)
wal 001374 -- top of stack
rm d=001230 -- !
#
step -- step (mtpi r6)
rpc d=004754 -- ! pc=next
rsp d=001372 -- ! sp=1372 (one pushed)
wal 001372 -- top of stack
rm d=000666 -- !
#
wal 005302 -- clean tainted memory
wm 000000 --
wal 005502 --
wm 000000 --
#
wps 000000 -- psw: cmode=pmode=0 (kernel)
#-----------------------------------------------------------------------------
C Setup code 22 [base 5000, use 50-57] (MMU ; run user mode code with I/D)
#
wal 177600 -- user I space DR
wmi 000002 -- slf=0; ed=0(up); acf=2(read-only)
wal 177620 -- user D space DR
wmi 000006 -- slf=0; ed=0(up); acf=6(w/r)
wal 177640 -- user I space AR
wmi 000053 -- 53 -> maps 0 -> 5300
wal 177660 -- user D space AR
wmi 000055 -- 55 -> maps 0 -> 5500
wal 177572 -- SSR0
wmi 000001 -- set enable bit
wal 172516 -- SSR3
wmi 000001 -- enable D space for user mode
#
wal 005000 -- code (kernel):
bwm 5
012746 -- mov #144000,-(sp) ;PS for RTI
174000 -- cmode=11,pmode=11,rset=1
012746 -- mov #0,-(sp) ;PC for RTI
000000 --
000002 -- rti
#-----
wal 000034 -- vector: 34 (TRAP)
bwm 2
005020 -- PC:5020
000340 -- PS: pri=7
#-----
wal 005020 -- code (kernel, trap 34):
bwm 4
011600 -- mov (sp),r0
006560 -- mfpi -2(r0)
177776
000000 -- halt
#-----
wal 000250 -- vector: 250 (MMU)
bwm 2
005040 -- PC:5040
000340 -- PS: pri=7
#-----
wal 005040 -- code (kernel, trap 4):
bwm 68
005337 -- dec @#5256
005256
001001 -- bne .+2
000000 -- halt
013700 -- mov ssr0,r0
177572
042700 -- bic #177741,r0 ; clear all but id+asn fields
177741
#5060
062700 -- add #177600,r0 ; user DR address base
177600
# 5 23 062710 0 -- add #400,(r0)
# 5 23 000400 0
105260 -- incb 1(r0) ; odd address IB access fails !!
000001
010025 -- mov r0,(r5)+
012025 -- mov (r0),(r5)+
013700 -- mov ssr1,r0
177574
#5100
010025 -- mov r0,(r5)+
012701 -- mov #2,r1
000002
052737 -- bis #004000,psw
004000
177776
005046 -- clr -(sp)
106506 -- mfpd sp
#5120
010546 -- mov r5,-(sp)
010446 -- mov r4,-(sp)
010346 -- mov r3,-(sp)
010246 -- mov r2,-(sp)
010146 -- mov r1,-(sp)
010046 -- mov r0,-(sp)
042737 -- bic #004000,psw
004000
#5140
177776
010002 -- L1: mov r0,r2
110003 -- movb r0,r3
042702 -- bic #177770,r2 ; mask regnum field
177770
006302 -- asl r2
060602 -- add sp,r2 ; address of reg on stack
006203 -- asr r3 ; shift delta field down 3 bit
#5160
006203 -- asr r3
006203 -- asr r3
160312 -- sub r3,(r2) ; correct register contents
000300 -- swap r0
077114 -- sob r1,L1 (.-12)
052737 -- bis #004000,psw
004000
177776
#5200
012600 -- mov (sp)+,r0
012601 -- mov (sp)+,r1
012602 -- mov (sp)+,r2
012603 -- mov (sp)+,r3
012604 -- mov (sp)+,r4
012605 -- mov (sp)+,r5
106606 -- mtpd sp
005726 -- tst (sp)+
#5220
042737 -- bic #004000,psw
004000
177776
013700 -- mov ssr2,r0
177576
010025 -- mov r0,(r5)+
010016 -- mov r0,(sp)
042737 -- bic #160000,ssr0 ; clear abort bits
#5240
160000
177572
000002 -- rti
000000 -- halt
#-----
wal 005256 -- data (kernel):
wmi 000003 -- stop at 3rd call of MMU handler
#-----
wal 005300 -- code (user):
bwm 8
012706 -- mov #100,sp
000100
005000 -- clr r0
012701 -- mov #074,r1
000074
062021 -- add (r0)+,(r1)+ ; r1 = 74
000137 -- jmp @#74
000074
#
wal 005374 -- .=5374
bwm 4
062021 -- add (r0)+,(r1)+ ; r1 = 76
062021 -- add (r0)+,(r1)+ ; r1 = 100
#5400
062021 -- add (r0)+,(r1)+ ; r1 = 102
104417 -- trap 17
#
wal 005500 -- data (user):
bwm 4
002001 -- mem_ud(0)=02001
002002 -- mem_ud(2)=02002
002003 -- mem_ud(4)=02003
002004 -- mem_ud(6)=02004
wal 005574 -- data (user):
bwm 4
000300 -- mem_ud(074)=0300
000300 -- mem_ud(076)=0300
000300 -- mem_ud(100)=0300
000300 -- mem_ud(102)=0300
#
C Exec code 22 (MMU ; run user mode code with I/D)
wr5 005260 -- r5=5260
wsp 001400 -- sp=1400
wpc 005000 -- pc=5000
sta -- start @ 5000
wtgo
rsp d=001372 -- ! sp
rpc d=005030 -- ! pc (halt in TRAP handler)
wal 001372 -- check stack (1372)
brm 3
d=104417 -- ! TRAP instruction
d=000104 -- ! PC trap
d=174000 -- ! PS trap
#
wal 005256 --
brm 9
d=000001 -- ! mem(5256) (mmu 3 - trap count)
d=177620 -- ! mem(5260) (1st trap: address fixed DR)
d=000406 -- ! mem(5262) (1st trap: new content of DR)
d=010420 -- ! mem(5264) (1st trap: ssr1: ra=0,2;rb=1,2)
d=000076 -- ! mem(5266) (1st trap: ssr2: pc)
d=177600 -- ! mem(5270) (2nd trap: address fixed DR)
d=000402 -- ! mem(5272) (2nd trap: new content of DR)
d=000000 -- ! mem(5274) (2nd trap: ssr1: none)
d=000100 -- ! mem(5276) (2nd trap: ssr2: pc)
#
wal 005574
brm 4
d=002301 -- ! mem(5574)=02301 was mem_ud(074)
d=002302 -- ! mem(5576)=02302 was mem_ud(076)
d=002303 -- ! mem(5600)=02303 was mem_ud(100)
d=002304 -- ! mem(5602)=02304 was mem_ud(102)
#
wal 000034 -- vector: 34 -> trap catcher again
bwm 2
000036 -- PC:36
000000 -- PS:0
wal 000250 -- vector: 250 -> trap catcher again
bwm 2
000252 -- PC:252
000000 -- PS:0
#
wps 000000 -- psw: cmode=pmode=0 (kernel)
#-----------------------------------------------------------------------------
C Setup code 23 [base 5700; use 57-63] (test cmp and conditional branch)
#
wal 005700 -- code test 1:
bwm 5
012012 -- mov (r0)+,(r2) ; load PSW from table
004737 -- jsr pc,@#6000
006000
077104 -- sob r1,-4
000000 -- halt
#
wal 005720 -- code test 2:
bwm 6
000230 -- spl 0
005720 -- tst (r0)+ ; verify tst response
004737 -- jsr pc,@#6000
006000
077104 -- sob r1,-4
000000 -- halt
#
wal 005740 -- code test 3:
bwm 6
000230 -- spl 0
022020 -- cmp (r0+),(r0)+ ; verify cmp response
004737 -- jsr pc,@#6000
006000
077104 -- sob r1,-4
000000 -- halt
#
# test 1 test 2 test 3
# - C V Z N < = > < = >
# code branch condition mask 1 2 3 4 5 1 2 3 1 2 3 4 5 6 7
# BNE if Z = 0 000004 y y y y y y y y y y y y
# BEQ if Z = 1 000010 y y y
# BGE if (N xor V) = 0 000020 y y y y y y y y y
# BLT if (N xor V) = 1 000040 y y y y y y
# BGT if (Z or (N xor V)) = 0 000100 y y y y y y
# BLE if (Z or (N xor V)) = 1 000200 y y y y y y y y y
# BPL if N = 0 000400 y y y y y y y y y y
# BMI if N = 1 001000 y y y y y
# BHI if (C or Z) = 0 002000 y y y y y y y y
# BLOS if (C or Z) = 1 004000 y y y y y y y
# BVC if V = 0 010000 y y y y y y y y y y y y
# BVS if V = 1 020000 y y y
# BCC if C = 0 (aka BHIS) 040000 y y y y y y y y y y y
# BCS if C = 1 (aka BLO) 100000 y y y y
#
wal 006000 -- code check:
bwm 63
011203 -- mov (r2),r3 ; save PSW
012704 -- mov #177774,r4 ; set pattern store
177774 --
010312 -- mov r3,(r2) ; restore PSW
001003 -- bne .+3
042704 -- bic #000004,r4
000004 --
010312 -- mov r3,(r2)
#6020
001403 -- beq .+3
042704 -- bic #000010,r4
000010 --
010312 -- mov r3,(r2)
002003 -- bge .+3
042704 -- bic #000020,r4
000020 --
010312 -- mov r3,(r2)
#6040
002403 -- blt .+3
042704 -- bic #000040,r4
000040 --
010312 -- mov r3,(r2)
003003 -- bgt .+3
042704 -- bic #000100,r4
000100 --
010312 -- mov r3,(r2)
#6060
003403 -- ble .+3
042704 -- bic #000200,r4
000200 --
010312 -- mov r3,(r2)
100003 -- bpl .+3
042704 -- bic #000400,r4
000400 --
010312 -- mov r3,(r2)
#6100
100403 -- bmi .+3
042704 -- bic #001000,r4
001000 --
010312 -- mov r3,(r2)
101003 -- bhi .+3
042704 -- bic #002000,r4
002000 --
010312 -- mov r3,(r2)
#6120
101403 -- blos .+3
042704 -- bic #004000,r4
004000 --
010312 -- mov r3,(r2)
102003 -- bvc .+3
042704 -- bic #010000,r4
010000 --
010312 -- mov r3,(r2)
#6140
102403 -- bvs .+3
042704 -- bic #020000,r4
020000 --
010312 -- mov r3,(r2)
103003 -- bcc .+3
042704 -- bic #040000,r4
040000 --
010312 -- mov r3,(r2)
#6160
103403 -- bcs .+3
042704 -- bic #100000,r4
100000 --
010312 -- mov r3,(r2)
010325 -- mov r3,(r5)+
010425 -- mov r4,(r5)+
000207 -- rts pc
#
wal 006200 -- data test 1:
bwm 5
000000 -- PSW - no cc
000001 -- PSW - C=1
000002 -- PSW - V=1
000004 -- PSW - Z=1
000010 -- PSW - N=1
#
wal 006220 -- data test 2:
bwm 3
177777 -- tst -1
000000 -- tst 0
000001 -- tst 1
#
wal 006230 -- data test 3:
bwm 14
000001 -- cmp 1,2
000002
000001 -- cmp 1,1
000001
#6240
000002 -- cmp 2,1
000001
177777 -- cmp -1,2
000002
000002 -- cmp 2,-1
177777
100000 -- cmp 100000,077777
077777
#6260
077777 -- cmp 077777,100000
100000
#
C Exec code 23 (test cmp and conditional branch)
C Exec test 23.1 (explict cc setting)
#
wr0 006200 -- r0=6200 (input data)
wr1 000005 -- r1=5
wr2 177776 -- r2=177776 (PS address)
wr5 006300 -- r5=6300 (output data)
wsp 001400 -- sp=1400
cres
stapc 005700 -- start @ 5700
wtgo
rr0 d=006212 -- ! r0
rr1 d=000000 -- ! r1
rr5 d=006324 -- ! r5
rsp d=001400 -- ! sp
rpc d=005712 -- ! pc
wal 006300 -- use BCC/BCS naming below
brm 10
d=000000 -- ! mem(6300) 1 PS: none
d=052524 -- ! mem(6302) 1 BNE,BGE,BGT,BPL,BHI,BVC,BCC
d=000001 -- ! mem(6304) 2 PS: C=1
d=114524 -- ! mem(6306) 2 BNE,BGE,BGT,BPL,BLOS,BVC,BCS
d=000002 -- ! mem(6310) 3 PS: V=1
d=062644 -- ! mem(6312) 3 BNE,BLT,BLE,BPL,BHI,BVS,BCC
d=000004 -- ! mem(6314) 4 PS: Z=1
d=054630 -- ! mem(6316) 4 BEQ,BGE,BLE,BPL,BLOS,BVC,BCC
d=000010 -- ! mem(6320) 5 PS: N=1
d=053244 -- ! mem(6322) 5 BNE,BLT,BLE,BMI,BHI,BVC,BCC
#
C Exec test 23.2 (tst testing)
#
wr0 006220 -- r0=6220 (input data)
wr1 000003 -- r1=3
wr2 177776 -- r2=177776 (PS address)
wr5 006330 -- sp=6330 (output data)
wsp 001400 -- sp=1400
cres
stapc 005720 -- start @ 5720
wtgo
rr0 d=006226 -- ! r0
rr1 d=000000 -- ! r1
rr5 d=006344 -- ! r5
rsp d=001400 -- ! sp
rpc d=005734 -- ! pc
wal 006330 -- use BHIS(BCC)/BLO(BLO) naming below
brm 6
d=000010 -- ! mem(6330) 1 PS: tst -1: N=1
d=053244 -- ! mem(6332) 1 BNE,BLT,BLE,BMI,BHI,BVC,BHIS
d=000004 -- ! mem(6334) 2 PS: tst 0: Z=1
d=054630 -- ! mem(6336) 2 BEQ,BGE,BLE,BPL,BLOS,BVC,BHIS
d=000000 -- ! mem(6340) 3 PS: tst 1: all 0
d=052524 -- ! mem(6342) 3 BNE,BGE,BGT,BPL,BHI,BVC,BHIS
#
C Exec test 23.3 (cmp testing)
#
wr0 006230 -- r0=6230 (input data)
wr1 000007 -- r1=7
wr2 177776 -- r2=177776 (PS address)
wr5 006344 -- sp=6344 (output data)
wsp 001400 -- sp=1400
cres
stapc 005740 -- start @ 5740
wtgo
rr0 d=006264 -- ! r0
rr1 d=000000 -- ! r1
rr5 d=006400 -- ! r5
rsp d=001400 -- ! sp
rpc d=005754 -- ! pc
wal 006344 -- cmp= S-D !
brm 14
d=000011 -- ! mem(6344) 1 PS: cmp 1,2: N=1,C=1 ok
d=115244 -- ! mem(6346) 1 BNE,BLT,BLE,BMI,BLOS,BVC,BLO
d=000004 -- ! mem(6350) 2 PS: cmp 1,1: Z=1 ok
d=054630 -- ! mem(6352) 2 BEQ,BGE,BLE,BPL,BLOS,BVC,BHIS
d=000000 -- ! mem(6354) 3 PS: cmp 2,1: none ok
d=052524 -- ! mem(6356) 3 BNE,BGE,BGT,BPL,BHI,BVC,BHIS
d=000010 -- ! mem(6360) 4 PS: cmp -1,2: N=1
d=053244 -- ! mem(6362) 4 BNE,BLT,BLE,BMI,BHI,BVC,BHIS ok
d=000001 -- ! mem(6364) 5 PS: cmp 2,-1: C=1
d=114524 -- ! mem(6366) 5 BNE,BGE,BGT,BPL,BLOS,BVC,BLO ok
d=000002 -- ! mem(6370) 6 PS: cmp 10..,07..: V=1
d=062644 -- ! mem(6372) 6 BNE,BLT,BLE,BPL,BHI,BVS,BHIS ok
d=000013 -- ! mem(6374) 7 PS: cmp 07..,10..: N=1,V=1,C=1
d=125124 -- ! mem(6376) 7 BNE,BGE,BGT,BMI,BLOS,BVS,BLO ok
#
#-----------------------------------------------------------------------------
C Setup code 24 [base 6400] (test MARK instruction)
#
wal 006400 -- code (main):
bwm 13
010546 -- mov r5,-(sp) ; push old r5 on stack
012746 -- mov #101,-(sp) ; push 1st parameter
000101
012746 -- mov #102,-(sp) ; push 2nd parameter
000102
012746 -- mov #103,-(sp) ; push 3rd parameter
000103
012746 -- mov #mark3,-(sp) ; push MARK 3
#6420
006403
010605 -- mov sp,r5 ; address of MARK N
004737 -- jsr pc,@#6440 ; call procedure
006440
000000 -- halt
#
# stack of procedure when called:
# addr content
# 576 12(sp) 10(r5) old r5
# 574 10(sp) 6(r5) param1
# 572 6(sp) 4(r5) param2
# 570 4(sp) 2(r5) param3
# 566 2(sp) (r5) mark 3
# 564 (sp) return pc
#
wal 006440 -- code (procedure):
bwm 7
016520 -- mov 6(r5),(r0)+ ; get 1st param
000006
016520 -- mov 4(r5),(r0)+ ; get 2nd param
000004
016520 -- mov 2(r5),(r0)+ ; get 3rd param
000002
000205 -- rts r5
#
C Exec code 24 (test MARK instruction)
#
wr0 006470 -- r0=6470
wr5 123456 -- r5=123456
wsp 001400 -- sp=1400
cres
stapc 006400 -- start @ 6400
wtgo
rr0 d=006476 -- ! r0=6476 (3 words written)
rr5 d=123456 -- ! r5 (restored)
rsp d=001400 -- ! sp
rpc d=006432 -- ! pc
wal 001364 -- check stack
brm 6
d=006430 -- ! mem(1364)
d=006403 -- ! mem(1366)
d=000103 -- ! mem(1370)
d=000102 -- ! mem(1372)
d=000101 -- ! mem(1374)
d=123456 -- ! mem(1376)
wal 006470 -- check stored values
brm 3
d=000101 -- ! mem(6470) (1st param)
d=000102 -- ! mem(6472) (2nd param)
d=000103 -- ! mem(6474) (3rd param)
#
# probably first and last time MARK is used. It's a bastard anyway.
#
#-----------------------------------------------------------------------------
C Setup code 25 [base 6500; use 65-66] (basic byte instruction and cc test)
#
wal 006500 -- code:
bwm 22
110124 -- movb r1,(r4)+ (#123, #333)
120124 -- cmpb r1,(r4)+ (#123, #333)
120224 -- cmpb r2,(r4)+ (#321, #111)
120124 -- cmpb r1,(r4)+ (#123, #123)
105024 -- clrb (r4)+ (#333)
130124 -- bitb r1,(r4)+ (#123, #11)
130124 -- bitb r1,(r4)+ (#123, #44)
140124 -- bicb r1,(r4)+ (#123, #333)
#6520
150124 -- bisb r1,(r4)+ (#123, #111)
105124 -- comb (r4)+ (#321)
105224 -- incb (r4)+ (#321)
105324 -- decb (r4)+ (#321)
105424 -- negb (r4)+ (#321)
105724 -- tstb (r4)+ (#321)
106024 -- rorb (r4)+ (#201) Cin=0; Cout=1
106024 -- rorb (r4)+ (#021) Cin=1; Cout=1
#6540
106124 -- rolb (r4)+ (#210) Cin=1; Cout=1
106224 -- asrb (r4)+ (#020)
106224 -- asrb (r4)+ (#220)
106324 -- aslb (r4)+ (#020)
106324 -- aslb (r4)+ (#220)
000000 -- halt
#
wal 000014 -- vector: 14
bwm 2
006560 -- PC:6560
000000 -- PS:0
#
wal 006560 -- code: (trap 14):
bwm 3
016625 -- mov 2(sp),(r5)+
000002
000006 -- rtt
#
wal 006600 -- data 1:
bwm 11
155733 -- (#333,#333)
051511 -- (#123,#111)
044333 -- (#11 ,#333)
155444 -- (#333,#44)
150511 -- (#321,#111)
150721 -- (#321,#321)
150721 -- (#321,#321)
010601 -- (#021,#201)
#6620
010210 -- (#020,#210)
010220 -- (#020,#220)
000220 -- (....,#220)
#
C Exec code 25 (basic byte instruction and cc test)
#
wr1 000123 -- r1=123
wr2 000321 -- r2=321
wr4 006600 -- r4=6600
wr5 006626 -- r5=6626
wsp 001374 -- sp=1374
wal 001374 -- setup stack with rtt return frame setting T flag
bwm 2
006500 -- start address (code 25 @ 6500)
000020 -- set T flag in PSW
cres
stapc 006564 -- start @ 6564 -> rtt -> 6500 from stack
wtgo
rr1 d=000123 -- ! r1=123
rr2 d=000321 -- ! r2=321
rr4 d=006625 -- ! r4=6625
rr5 d=006700 -- ! r5=6700
rsp d=001400 -- ! sp=1400
rpc d=006554 -- ! pc=6554
wal 006600
brm 11
d=155523 -- ! mem(6600)=123; movb r1,(r4)+ (#123, #333)
# ! mem(6601)=333; cmpb r1,(r4)+ (#123, #333)
d=051511 -- ! mem(6602)=111; cmpb r1,(r4)+ (#321, #111)
# ! mem(6603)=123; cmpb r1,(r4)+ (#123, #123)
d=044000 -- ! mem(6604)=000; clrb (r4)+ (#333)
# ! mem(6605)=011; bitb r1,(r4)+ (#123, #11)
d=104044 -- ! mem(6606)=044; bitb r1,(r4)+ (#123, #44)
# ! mem(6607)=210; bicb r1,(r4)+ (#123, #333)
d=027133 -- ! mem(6610)=133; bisb r1,(r4)+ (#123, #111)
# ! mem(6611)=056; comb (r4)+ (#321)
d=150322 -- ! mem(6612)=322; incb (r4)+ (#321)
# ! mem(6613)=320; decb (r4)+ (#321)
d=150457 -- ! mem(6614)=057; negb (r4)+ (#321)
# ! mem(6615)=321; tstb (r4)+ (#321)
d=104100 -- ! mem(6616)=100; rorb (r4)+ (#201) Cout=1
# ! mem(6617)=210; rorb (r4)+ (#021) Cout=1
d=004021 -- ! mem(6620)=021; rolb (r4)+ (#210) Cout=1
# ! mem(6621)=010; asrb (r4)+ (#020)
d=020310 -- ! mem(6622)=310; asrb (r4)+ (#220)
# ! mem(6623)=040; aslb (r4)+ (#020)
d=000040 -- ! mem(6624)=040; aslb (r4)+ (#220)
#
wal 006626 -- NZVC
brm 21
d=000020 -- ! mem(6626)=0000; movb r1,(r4)+ (#123, #333)
d=000021 -- ! mem(6630)=000C; cmpb r1,(r4)+ (#123, #333)
d=000030 -- ! mem(6632)=N000; cmpb r1,(r4)+ (#321, #111)
d=000024 -- ! mem(6634)=0Z00; cmpb r1,(r4)+ (#123, #123)
d=000024 -- ! mem(6636)=0Z00; clrb (r4)+ (#333)
d=000020 -- ! mem(6640)=0000; bitb r1,(r4)+ (#123, #11)
d=000024 -- ! mem(6642)=0Z00; bitb r1,(r4)+ (#123, #44)
d=000030 -- ! mem(6644)=N000; bicb r1,(r4)+ (#123, #333)
d=000020 -- ! mem(6646)=0000; bisb r1,(r4)+ (#123, #111)
d=000021 -- ! mem(6650)=000C; comb (r4)+ (#321)
d=000031 -- ! mem(6652)=N00C; incb (r4)+ (#321) keep C!
d=000031 -- ! mem(6654)=N00C; decb (r4)+ (#321) keep C!
d=000021 -- ! mem(6656)=000C; negb (r4)+ (#321)
d=000030 -- ! mem(6660)=N000; tstb (r4)+ (#321)
d=000023 -- ! mem(6662)=00VC; rorb (r4)+ (#201)
d=000031 -- ! mem(6664)=N00C; rorb (r4)+ (#021)
d=000023 -- ! mem(6666)=00VC; rolb (r4)+ (#210)
d=000020 -- ! mem(6670)=0000; asrb (r4)+ (#020)
d=000032 -- ! mem(6672)=N0V0; asrb (r4)+ (#220)
d=000020 -- ! mem(6674)=0000; aslb (r4)+ (#020)
d=000023 -- ! mem(6676)=00VC; aslb (r4)+ (#220)
#
cres -- console reset (to clear T flag)
wal 000014 -- vector: 14 -> trap catcher again
bwm 2
000016 -- PC:16
000000 -- PS:0
#-----------------------------------------------------------------------------
C Setup code 26 [base 6700; use 67-70] (address modes torture tests)
#
wal 006700 -- code test 1:
bwm 5
012020 -- mov (r0)+,(r0)+
062020 -- add (r0)+,(r0)+
014141 -- mov -(r1),-(r1)
064141 -- add -(r1),-(r1)
#6710
000000 -- halt
#-----
wal 006720 -- code test 2:
bwm 8
016767 -- mov a(pc),b(pc)
000014 -- here pc=6724, target@6740 --> index=14
000014 -- here pc=6726, target@6742 --> index=14
066767 -- add c(pc),d(pc)
#6730
000012 -- here pc=6732, target@6744 --> index=12
000012 -- here pc=6734, target@6746 --> index=12
000000 -- halt
000000 -- halt
#
wal 006740 -- data (pc relative) for test 2:
bwm 4
006740 -- target for mov a(pc)
006742 -- target for ,b(pc)
000011 -- target for add c(pc)
006746 -- target for ,d(pc)
#-----
wal 006750 -- code test 3:
bwm 12
012727 -- mov #1,#0
000001
000000
062727 -- add #1,#2
#6760
000001
000002
016767 -- mov -14(pc),2(pc)
177764 -- pc here: 6770: read dst of mov #1,#0 (@6754)
000002 -- pc here: 6772: write src of add #0,r0 (@6774)
062700 -- add #0,r0
000000
000000 -- halt
#-----
wal 007000 -- code test 4:
bwm 8
005200 -- inc r0
010001 -- mov r0,r1
010702 -- mov pc,r2
005007 -- clr pc
000000 -- halt
000000 -- halt
005203 -- L1: inc r3
000000 -- halt
#-----
wal 000000 -- code test 4 (handler at address=0):
bwm 2
000137 -- jmp @#L1
007014
#-----
wal 007020 -- code test 5:
bwm 11
012707 -- mov #L2,pc
007032
000000 -- halt
000000 -- halt
000000 -- halt
062707 -- L2: add #2,pc
000002
005201 -- inc r1
#7040
005201 -- inc r1
005201 -- inc r1
000000 -- halt
#-----
wal 007060 -- data for test 1 (r0)+ part:
bwm 4
000111
000222
000333
000444
wal 007070 -- data for test 1 -(r1) part:
bwm 4
000111
000222
000333
000444
C Exec code 26 (address modes torture tests)
C Exec test 26.1 (test src-dst update hazards with (r0)+,(r0)+ ect):
#
wr0 007060 -- r0=7060 (input data for (r0)+...)
wr1 007100 -- r1=7100 (input data for -(r1)...)
wsp 001400 -- sp=1400
cres
stapc 006700 -- start @ 6700
wtgo
rr0 d=007070 -- ! r0
rr1 d=007070 -- ! r1
rpc d=006712 -- ! pc
wal 007060 --
brm 4
d=000111 -- ! mem(7060)
d=000111 -- ! mem(7062)
d=000333 -- ! mem(7064)
d=000777 -- ! mem(7066)
wal 007070 --
brm 4
d=000333 -- ! mem(7070)
d=000222 -- ! mem(7072)
d=000444 -- ! mem(7074)
d=000444 -- ! mem(7076)
C Exec test 26.2 (test indexed mode with pc (mode 67)):
#
wsp 001400 -- sp=1400
cres
stapc 006720 -- start @ 6720
wtgo
rpc d=006736 -- ! pc
wal 006740 --
brm 4
d=006740 -- ! mem(6740)
d=006740 -- ! mem(6742)
d=000011 -- ! mem(6744)
d=006757 -- ! mem(6746)
C Exec test 26.3 (test (pc)+ as dst):
#
wr0 000111 -- r0=0111
wsp 001400 -- sp=1400
cres
stapc 006750 -- start @ 6750
wtgo
rr0 d=000112 -- ! r0
rpc d=007000 -- ! pc
wal 006752 --
brm 2
d=000001 -- ! mem(6752) src mov #1,#0
d=000001 -- ! mem(6754) dst mov #1,#0
wal 006760 --
brm 2
d=000001 -- ! mem(6760) src add #1,#2
d=000003 -- ! mem(6762) dst add #1,#2
wal 006774 -- !
rmi d=000001 -- ! mem(6774) dst mov -12(pc),2(pc)
C Exec test 26.4 (test pc as dst in clr):
#
wr0 000100 -- r0=0100
wr1 000110 -- r1=0110
wr2 000120 -- r2=0120
wr3 000130 -- r3=0130
wsp 001400 -- sp=1400
cres
stapc 007000 -- start @ 7000
wtgo
rr0 d=000101 -- ! r0
rr1 d=000101 -- ! r1
rr2 d=007006 -- ! r2 (pc after mov pc,r2)
rr3 d=000131 -- ! r3
rpc d=007020 -- ! pc
# cleanup 'vector 0':
wal 000000
bwm 2
000000
000000
C Exec test 26.5 (test pc as dst in mov and add):
#
wr1 000000 -- r1=0
wsp 001400 -- sp=1400
cres
stapc 007020 -- start @ 7020
wtgo
rr1 d=000002 -- ! r1
rpc d=007046 -- ! pc
#-----------------------------------------------------------------------------
C Setup code 27 [base 7100; use 71-101] (test ASH/ASHC instruction)
#
wal 007100 -- code test 1 (ash)
bwm 7
000230 -- spl 0
012004 -- L1: mov (r0)+,r4 -- load low
072420 -- ash (r0)+,r4 -- shift
011321 -- mov (r3),(r1)+ -- store psw
010421 -- mov r4,(r1)+ -- store low
077205 -- sob r2,L1 (.-5)
000000 -- halt
#-----
wal 007120 -- code test 2 (ashc even)
bwm 9
000230 -- spl 0
012004 -- L1: mov (r0)+,r4 -- load high
012005 -- mov (r0)+,r5 -- load low
073420 -- ashc (r0)+,r4 -- shift
011321 -- mov (r3),(r1)+ -- store psw
010421 -- mov r4,(r1)+ -- store high
010521 -- mov r5,(r1)+ -- store low
077207 -- sob r2,L1 (.-7)
#7140
000000 -- halt
#-----
wal 007150 -- code test 3 (ashc odd)
bwm 7
000230 -- spl 0
012005 -- L1: mov (r0)+,r5 -- load low
073520 -- ashc (r0)+,r5 -- shift
011321 -- mov (r3),(r1)+ -- store psw
#7160
010521 -- mov r5,(r1)+ -- store low
077205 -- sob r2,L1 (.-5)
000000 -- halt
#-----
wal 007200 -- data 1:
bwm 24
000200 -- (000200, +1)
000001 --
000200 -- (000200, -1)
177777 --
000200 -- (000200, +7)
000007 --
000200 -- (000200, +8)
000010 --
#7220
000200 -- (000200, +9)
000011 --
000200 -- (000200, -7)
177771 --
100000 -- (100000, 0)
000000 --
000000 -- (000000, 0)
000000 --
#7240
000200 -- (000200, -8)
177770 --
000200 -- (000200, 0)
000000 --
100000 -- (100000, -6)
177772 --
040000 -- (040000, +1)
000001 --
#-----
wal 007300 -- data 2:
bwm 30
000020 -- (000020,000200, +1)
000200 --
000001 --
000020 -- (000020,000200, -1)
000200 --
177777 --
000020 -- (000020,000200, +7)
000200 --
#7320
000007 --
000020 -- (000020,000200, +8)
000200 --
000010 --
000020 -- (000020,000200, +9)
000200 --
000011 --
000000 -- (000000,000200, +23)
#7340
000200 --
000027 --
000000 -- (000000,000200, +24)
000200 --
000030 --
000000 -- (000000,000200, +25)
000200 --
000031 --
#7360
000020 -- (000020,000200, -5)
000200 --
177773 --
000020 -- (000020,000200, -8)
000200 --
177770 --
#-----
wal 007440 -- data 3:
bwm 6
000200 -- (000200, +1)
000001 --
000200 -- (000200, -1)
177777 --
000201 -- (000201, -1)
177777 --
#
C Exec code 27 (test ASH/ASHC instruction)
C Exec test 27.1 (test ash)
#
wr0 007200 -- r0=7200 (input data)
wr1 007500 -- r1=7500 (output data)
wr2 000014 -- r2=14 (test count)
wr3 177776 -- r3=177776 (#PSW)
wsp 001400 -- sp=1400
cres
stapc 007100 -- start @ 7100
wtgo
rr0 d=007260 -- ! r0
rr1 d=007560 -- ! r1
rpc d=007116 -- ! pc
wal 007500 --
brm 24
d=000000 -- ! mem(7500) ash +1, 000200 -> nzvc=0
d=000400 -- ! mem(7502)
d=000000 -- ! mem(7504) ash -1, 000200 -> nzvc=0
d=000100 -- ! mem(7506)
d=000000 -- ! mem(7510) ash +7, 000200 -> nzvc=0
d=040000 -- ! mem(7512)
d=000012 -- ! mem(7514) ash +8, 000200 -> n1,z0,v1,c0
d=100000 -- ! mem(7516)
d=000007 -- ! mem(7520) ash +9, 000200 -> n0,z1,v1,c1
d=000000 -- ! mem(7522)
d=000000 -- ! mem(7524) ash -7, 000200 -> nzvc=0
d=000001 -- ! mem(7526)
d=000010 -- ! mem(7530) ash 0, 100000 -> n1,z0,v0,c0
d=100000 -- ! mem(7532)
d=000004 -- ! mem(7534) ash 0, 000000 -> n0,z1,v0,c0
d=000000 -- ! mem(7536)
d=000005 -- ! mem(7540) ash -8, 000200 -> n1,z1,v0,c1
d=000000 -- ! mem(7542)
d=000000 -- ! mem(7544) ash 0, 000200 -> n0,z0,v0,c0
d=000200 -- ! mem(7546)
d=000010 -- ! mem(7550) ash -6, 100000 -> n1,z0,v0,c0
d=177000 -- ! mem(7552)
d=000012 -- ! mem(7554) ash +1, 040000 -> n1,z0,v1,c0
d=100000 -- ! mem(7556)
#----
C Exec test 27.2 (test ashc even)
#
wr0 007300 -- r0=7300 (input data)
wr1 007600 -- r1=7600 (output data)
wr2 000012 -- r2=12 (test count)
wr3 177776 -- r3=177776 (#PSW)
wsp 001400 -- sp=1400
cres
stapc 007120 -- start @ 7120
wtgo
rr0 d=007374 -- ! r0
rr1 d=007674 -- ! r1
rpc d=007142 -- ! pc
wal 007600 --
brm 30
d=000000 -- ! mem(7600) ashc +1, 000020,000200 -> nzvc=0
d=000040 -- ! mem(7602)
d=000400 -- ! mem(7604)
d=000000 -- ! mem(7606) ashc -1, 000020,000200 -> nzvc=0
d=000010 -- ! mem(7610)
d=000100 -- ! mem(7612)
d=000000 -- ! mem(7614) ashc +7, 000020,000200 -> nzvc=0
d=004000 -- ! mem(7616)
d=040000 -- ! mem(7620)
d=000000 -- ! mem(7622) ashc +8, 000020,000200 -> nzvc=0
d=010000 -- ! mem(7624)
d=100000 -- ! mem(7626)
d=000000 -- ! mem(7630) ashc +9, 000020,000200 -> nzvc=0
d=020001 -- ! mem(7632)
d=000000 -- ! mem(7634)
d=000000 -- ! mem(7636) ashc +23, 000000,000200 -> nzvc=0
d=040000 -- ! mem(7640)
d=000000 -- ! mem(7642)
d=000012 -- ! mem(7644) ashc +24, 000000,000200 -> n1z0v1c0
d=100000 -- ! mem(7646)
d=000000 -- ! mem(7650)
d=000007 -- ! mem(7652) ashc +25, 000000,000200 -> n0z1v1c1
d=000000 -- ! mem(7654)
d=000000 -- ! mem(7656)
d=000000 -- ! mem(7660) ashc -5, 000020,000200 -> nzvc=0
d=000000 -- ! mem(7662)
d=100004 -- ! mem(7664)
d=000001 -- ! mem(7666) ashc -8, 000020,000200 -> n0z0v0c1
d=000000 -- ! mem(7670)
d=010000 -- ! mem(7672)
#----
C Exec test 27.3 (test ashc odd)
#
wr0 007440 -- r0=7440 (input data)
wr1 007740 -- r1=7740 (output data)
wr2 000003 -- r2=3 (test count)
wr3 177776 -- r3=177776 (#PSW)
wsp 001400 -- sp=1400
cres
stapc 007150 -- start @ 7150
wtgo
rr0 d=007454 -- ! r0
rr1 d=007754 -- ! r1
rpc d=007166 -- ! pc
wal 007740 --
brm 6
d=000000 -- ! mem(7740) ashc +1, 000200 -> nzvc=0
d=000400 -- ! mem(7742)
d=000000 -- ! mem(7744) ashc -1, 000200 -> nzvc=0
d=000100 -- ! mem(7746)
d=000001 -- ! mem(7750) ashc -1, 000201 -> n0z0v0c1
d=100100 -- ! mem(7752)
#-----------------------------------------------------------------------------
C Setup code 30 [base 10200; use 102-103] (test MUL instruction)
#
wal 010200 -- code test 1 (mul even)
bwm 8
000230 -- spl 0
012004 -- L1: mov (r0)+,r4 -- load p1
070420 -- mul (r0)+,r4 -- mul
011321 -- mov (r3),(r1)+ -- store psw
010421 -- mov r4,(r1)+ -- store p_high
010521 -- mov r5,(r1)+ -- store p_low
077206 -- sob r2,L1 (.-6)
000000 -- halt
#-----
wal 010220 -- code test 2 (mul odd)
bwm 7
000230 -- spl 0
012005 -- L1: mov (r0)+,r5 -- load p1
070520 -- mul (r0)+,r5 -- mul
010521 -- mov r5,(r1)+ -- store p_low
060403 -- add r4,r3 -- check r4
077205 -- sob r2,L1 (.-5)
000000 -- halt
#
# 31022 074456 * 9562 022532 -> 296632364 010656,040054
# 18494 044076 * -24041 121027 -> -444614254 162577,134622
# -12549 147373 * 2397 004535 -> -30079953 177065,002057
# -20493 127763 * -23858 121316 -> 488921994 016444,055612
#
# 105 000151 * 198 000306 -> 20790 000000,050466
# 233 000351 * -94 177642 -> -21902 177777,125162
# 186 000272 * -205 177463 -> -38130 177777,065416
#
wal 010240 -- data 1:
bwm 16
074456 --
022532 --
044076 --
121027 --
147373 --
004535 --
127763 --
121316 --
#10260
000151 --
000306 --
000351 --
177642 --
000272 --
177463 --
000000 --
000272 --
#
C Exec code 30 (test MUL instruction)
C Exec test 30.1 (test mul even)
#
wr0 010240 -- r0=10240 (input data)
wr1 010300 -- r1=10300 (output data)
wr2 000010 -- r2=10 (test count)
wr3 177776 -- r3=177776 (#PSW)
wsp 001400 -- sp=1400
cres
stapc 010200 -- start @ 10200
wtgo
rr0 d=010300 -- ! r0
rr1 d=010360 -- ! r1
rpc d=010220 -- ! pc
wal 010300 --
brm 24
d=000001 -- ! mem(10300) mul 074456,022532 -> n0z0v0c1
d=010656 -- ! mem(10302)
d=040054 -- ! mem(10304)
d=000011 -- ! mem(10306) mul 044076,121027 -> n1z0v0c1
d=162577 -- ! mem(10310)
d=134622 -- ! mem(10312)
d=000011 -- ! mem(10314) mul 147373,004535 -> n1z0v0c1
d=177065 -- ! mem(10316)
d=002057 -- ! mem(10320)
d=000001 -- ! mem(10322) mul 127763,121316 -> n0z0v0c1
d=016444 -- ! mem(10324)
d=055612 -- ! mem(10326)
d=000000 -- ! mem(10330) mul 000151,000306 -> n0z0v0c0
d=000000 -- ! mem(10332)
d=050466 -- ! mem(10334)
d=000010 -- ! mem(10336) mul 000351,177642 -> n1z0v0c0
d=177777 -- ! mem(10340)
d=125162 -- ! mem(10342)
d=000011 -- ! mem(10344) mul 000272,177463 -> n1z0v0c1
d=177777 -- ! mem(10346)
d=065416 -- ! mem(10350)
d=000004 -- ! mem(10352) mul 000000,000272 -> n0z1v0c0
d=000000 -- ! mem(10354)
d=000000 -- ! mem(10356)
#----
C Exec test 30.2 (test mul odd)
#
wr0 010240 -- r0=10240 (input data)
wr1 010360 -- r1=10300 (output data)
wr2 000010 -- r2=10 (test count)
wr3 000000 -- r3=0
wr4 000000 -- r4=0
wsp 001400 -- sp=1400
cres
stapc 010220 -- start @ 10220
wtgo
rr0 d=010300 -- ! r0
rr1 d=010400 -- ! r1
rr3 d=000000 -- ! r3
rpc d=010236 -- ! pc
wal 010360 --
brm 8
d=040054 -- ! mem(10360)
d=134622 -- ! mem(10362)
d=002057 -- ! mem(10364)
d=055612 -- ! mem(10366)
d=050466 -- ! mem(10370)
d=125162 -- ! mem(10372)
d=065416 -- ! mem(10374)
d=000000 -- ! mem(10376)
#
#-----------------------------------------------------------------------------
C Setup code 31 [base 10400; use 104-110] (test DIV instruction, also ADC,SXT)
# Note: test 2 uses sbc too, but if div/div work correctly we have always
# C=0 for sbc, so sbc isn't tested. adc has C=0 or C=1 though.
#
wal 010400 -- code test 1
bwm 8
012004 -- L1: mov (r0)+,r4 -- load dd high
012005 -- mov (r0)+,r5 -- load dd low
071420 -- div (r0)+,r4 -- div
011321 -- mov (r3),(r1)+ -- store psw
010421 -- mov r4,(r1)+ -- store q
010521 -- mov r5,(r1)+ -- store r
077207 -- sob r2,L1 (.-7)
000000 -- halt
#-----
wal 010420 -- code test 2
bwm 24
012146 -- L1: mov (r1)+,-(sp) -- save psw on stack
016002 -- mov 4(r0),r2 -- load divisor
000004
070221 -- mul (r1)+,r2 -- multiply with quotient
061103 -- add (r1),r3 -- add reminder
005502 -- adc r2
005721 -- tst (r1)+
006704 -- sxt r4
#10440
060402 -- add r4,r2
166003 -- sub 2(r0),r3 -- subtract divident
000002
005602 -- sbc r2
161002 -- sub (r0),r2
001002 -- bne L2 (.+2) -- error if !=0
005703 -- tst r3
001404 -- beq L3 (.+4) -- error if !=0
#10460
032726 -- L2: bit #3,(sp)+ -- check V,C bits
000003
001001 -- bne L3 (.+1) -- if V or C =1, ignore
000000 -- halt
062700 -- L3: add #6,r0 --
000006 --
077527 -- sob r5,L1 (.-23)
000000 -- halt
# r q
# 6249 014151 * 9158 021706 + 4989 011575 -> 57233331 001551,047663 y n
# 5194 012112 * -23807 121401 + -3990 170152 -> -123657548 174241,021264 n y
# -19943 131031 * 27112 064750 + -16037 140533 -> -540710653 157705,064403 y n
# -20493 127763 * -23858 121316 + 10744 024770 -> 488932738 016444,102602 y y
#
# -12549 147373 * 2397 004535 + -11187 152115 -> -30091140 177064,154174 n n
# 22620 054134 * -9272 155710 + -19907 131075 -> -209752547 171577,067035 y y
# 10723 024743 * 7931 017373 + 9824 023140 -> 85053937 002421,150761 n n
# -3548 171044 * -15677 141303 + 3019 005713 -> 55625015 001520,142467 n y
#
## 1 000001 * -32767 100001 + 0 000000 -> -32767 177777,100001 V=0
## -1 177777 * 32767 077777 + 0 000000 -> -32767 177777,100001 V=0
# 1 000001 * -32768 100000 + 0 000000 -> -32768 177777,100000 V=1
# -1 177777 * ...... ...... + 0 000000 -> -32768 177777,100000 V=1
#
# 32767 077777 * 32767 077777 + 32766 077776 -> 1073709055 037777,077777 V=0
# 32767 077777 * ............ + ............ -> 1073709056 037777,100000 V=1
# 32767 077777 * -32767 100001 + -32766 100002 ->-1073709055 140000,100001 V=0
# 32767 077777 * ............ + ............ ->-1073709056 140000,100000 V=1
#
# 32767 077777 * ............ + ............ -> 1073741824 040000,000000 V=1
##32767 077777 * ............ + ............ ->-2147483648 100000,000000 V=1
#
#
wal 010500 -- data 1:
bwm 63
000000 -- (000000,000042, 000005) 34/ 5 -> q: 6 r: 4
000042 --
000005 --
000000 -- (000000,000042, 177773) 34/-5 -> q:-6 r: 4
000042 --
177773 --
177777 -- (177777,177736, 000005) -34/ 5 -> q:-6 r:-4
177736 --
#010520
000005 --
177777 -- (177777,177736, 177773) -34/-5 -> q: 6 r:-4
177736 --
177773 --
001551 -- (001551,047663, 014151) 57233331 / 6249
047663 -- -> q: 9158 r: 4989
014151 --
174241 -- (174241,021264, 012112) -123657548 / 5194
#010540
021264 -- -> q: -23807 r: -3990
012112 --
157705 -- (157705,064403, 131031) -540710653 / -19943
064403 -- -> q: 27112 r: -16037
131031 --
016444 -- (016444,102602, 127763) 488932738 / -20493
102602 -- -> q: -23858 r: 10744
127763 --
#010560
177064 -- (177064,154174, 147373) -30091140 / -12549
154174 -- -> q: 2397 r: -11187
147373 --
171577 -- (171577,067035, 054134) -209752547 / 22620
067035 -- -> q: -9272 r: -19907
054134 --
002421 -- (002421,150761, 024743) 85053937 / 10723
150761 -- -> q: 7931 r: 9824
#010600
024743 --
001520 -- (001520,142467, 171044) 55625015 / -3548
142467 -- -> q: -15677 r: 3019
171044 --
001520 -- (001520,142467,000000) 55625015 / 0
142467 --
000000 --
000000 -- (000000,000000,021706) 0 / 9158
#010620
000000 --
021706 --
177777 -- (177777,100000,000001) -32768 / 1
100000 --
000001 --
177777 -- (177777,100000,177777) -32768 / -1
100000 --
177777 --
#010640
037777 -- (037777,077777,077777) 1073709055 / 32767
077777 --
077777 --
037777 -- (037777,100000,077777) 1073709056 / 32767
100000 --
077777 --
140000 -- (140000,100001,077777) -1073709055 / 32767
100001 --
#010660
077777 --
140000 -- (140000,100000,077777) -1073709056 / 32767
100000 --
077777 --
040000 -- (040000,000000,077777) 1073741824 / 32767
000000 --
077777 --
#
C Exec code 31 (test DIV instruction, also ADC,SXT)
C Exec test 31.1 (test div)
#
wr0 010500 -- r0=10500 (input data)
wr1 010700 -- r1=10700 (output data)
wr2 000025 -- r2=25 (test count)
wr3 177776 -- r3=177776 (#PSW)
wsp 001400 -- sp=1400
cres -- console reset ; do reset; cont to start with
wps 000000 -- clear psw ; psw cc code dump below
wpc 010400 -- pc=10400
sta -- start @ 10400
wtgo
rr0 d=010676 -- ! r0
rr1 d=011076 -- ! r1
rpc d=010420 -- ! pc
wal 010700 --
brm 63
d=000000 -- ! mem(10700) div 000000, 000042,000005 -> n0z0v0c0
d=000006 -- ! mem(10702) 34/ 5 -> 6,4
d=000004 -- ! mem(10704)
d=000010 -- ! mem(10706) div 000000,000042, 177773 -> n1z0v0c0
d=177772 -- ! mem(10710) 34/-5 -> -6,4
d=000004 -- ! mem(10712)
d=000010 -- ! mem(10714) div 177777,177736, 000005 -> n1z0v0c0
d=177772 -- ! mem(10716) -34/ 5 -> -6,-4
d=177774 -- ! mem(10720)
d=000000 -- ! mem(10722) div 177777,177736, 177773 -> n0z0v0c0
d=000006 -- ! mem(10724) -34/-5 -> 6,-4
d=177774 -- ! mem(10726)
d=000000 -- ! mem(10730) div 001551,047663, 014151 -> n0z0v0c0
d=021706 -- ! mem(10732) 57233331/6249 -> 9158,4989
d=011575 -- ! mem(10734)
d=000010 -- ! mem(10736) div 174241,021264, 012112 -> n1z0v0c0
d=121401 -- ! mem(10740) -123657548/5194 -> -23807,-3990
d=170152 -- ! mem(10742)
d=000000 -- ! mem(10744) div 157705,064403, 131031 -> n0z0v0c0
d=064750 -- ! mem(10746) -540710653/-19943 -> 27112,-16037
d=140533 -- ! mem(10750)
d=000010 -- ! mem(10752) div 016444,102602, 127763 -> n1z0v0c0
d=121316 -- ! mem(10754) 488932738/-20493 -> -23858, 10744
d=024770 -- ! mem(10756)
d=000000 -- ! mem(10760) div 177064,154174, 147373 -> n0z0v0c0
d=004535 -- ! mem(10762) -30091140/-12549 -> 2397,-11187
d=152115 -- ! mem(10764)
d=000010 -- ! mem(10766) div 171577,067035, 054134 -> n1z0v0c0
d=155710 -- ! mem(10770) -209752547/22620 -> -9272,-19907
d=131075 -- ! mem(10772)
d=000000 -- ! mem(10774) div 002421,150761, 024743 -> n0z0v0c0
d=017373 -- ! mem(10776) 85053937/10723 -> 7931,9824
d=023140 -- ! mem(11000)
d=000010 -- ! mem(11002) div 001520,142467, 171044 -> n1z0v0c0
d=141303 -- ! mem(11004) 55625015/-3548 -> -15677,3019
d=005713 -- ! mem(11006)
d=000007 -- ! mem(11010) div 001520,142467,000000 -> n0z1v1c1
d=001520 -- ! mem(11012) 55625015/0 -> V=1, keep regs
d=142467 -- ! mem(11014)
d=000004 -- ! mem(11016) div 000000,000000,021706 -> n0z1v1c0
d=000000 -- ! mem(11020) 0/9158 -> 0,0
d=000000 -- ! mem(11022)
d=000010 -- ! mem(11024) div 177777,100000,000001->n1z0v1c0
d=100000 -- ! mem(11026) -32768/1 -> -32768,0
d=000000 -- ! mem(11030)
d=000002 -- ! mem(11032) div 177777,100000,177777 -> n0z0v1c0 ?? 2
d=177777 -- ! mem(11034) -32768/-1 -> overflow
d=100000 -- ! mem(11036)
d=000000 -- ! mem(11040) div 037777,077777,077777 -> n0z0v0c0
d=077777 -- ! mem(11042) 1073709055/32767 -> 32767,32766
d=077776 -- ! mem(11044)
d=000002 -- ! mem(11046) div 037777,100000,077777 -> n0z0v1c0
d=037777 -- ! mem(11050) 1073709056/32767 -> overflow
d=100000 -- ! mem(11052)
d=000010 -- ! mem(11054) div 140000,100001,077777 -> n1z0v0c0
d=100001 -- ! mem(11056) -1073709055/32767 -> -32767,-32766
d=100002 -- ! mem(11060)
d=000010 -- ! mem(11062) div 140000,100000,077777->n1z0v1c0
d=100000 -- ! mem(11064) -1073709056/32767 -> -32768,0
d=000000 -- ! mem(11066)
d=000002 -- ! mem(11070) div 040000,000000,077777 -> n0z0v1c0
d=040000 -- ! mem(11072) 1073741824/32767 -> overflow
d=000000 -- ! mem(11074)
#
# simh notes:
# 1. a quotient of 100000 leads to an overflow (V=1) on the W11
# simh will not indicate overflow and returns q=100000
#
#----
C Exec test 31.2 (test mul after div)
#
wr0 010500 -- r0=10500 (input data from DIV)
wr1 010700 -- r1=10700 (output data from DIV)
wr5 000016 -- r5=16 (test count)
wsp 001400 -- sp=1400
cres
stapc 010420 -- start @ 10420
wtgo
rr0 d=010624 -- ! r0
rr1 d=011024 -- ! r1
rr2 d=000000 -- ! r2
rr3 d=000000 -- ! r3
rr5 d=000000 -- ! r5
rpc d=010500 -- ! pc
#-----------------------------------------------------------------------------
C Setup code 32 [base 11100; use 111-112] (PIRQ test)
# The code will exercise all 7 pirq interrupt levels:
# set 1+3 -> handle 3, set 7 -> handle 7, set 6+4 -> handle 6
# -> handle 4, set 5+2 -> handle 5 -> handle 2 > handle 1
#
wal 011100 -- code:
bwm 14
000237 -- spl 7
011425 -- mov (r4),(r5)+ ; save PSW
012713 -- mov #1000,(r3) ; set PIRQ 1
001000
011325 -- mov (r3),(r5)+ ; save PIRQ
112763 -- movb #12,1(r3) ; set PIRQ 1+3
000012
000001
#11120
011325 -- mov (r3),(r5)+ ; save PIRQ
000232 -- spl 2 ; now pri=2
000240 -- nop ; allow interrupt to happen
000230 -- spl 0 ; now pri=0
#11130
000240 -- nop ; allow interrupt to happen
000000 -- halt
#-----
wal 000240 -- vector: 240
bwm 2
011134 -- PC:11134
000340 -- PS:pri=7
#-----
wal 011134 -- code: (vector 240)
bwm 18
011300 -- mov (r3),r0 ; get pirq
010625 -- mov sp,(r5)+ ; save sp
#11140
010025 -- mov r0,(r5)+ ; save pirq
110014 -- movb r0,(r4) ; PSW=PIRQ (sets priority)
042700 -- bic #177761,r0 ; mask out index bits
177761
010001 -- mov r0,r1 ; r0 is word index (pri*2)
006201 -- asr r1 ; r1 is byte index (pri*1)
012702 -- mov #400,r2
000400
#11160
072201 -- ash r1,r2 ; r2 = 1<<(pri)
040213 -- bic r2,(r3) ; clear current level in pirq
010246 -- mov r2,-(sp) ; save pirq level mask
056013 -- bis 11200(r0),(r3) ; trigger new pirq's
011200
000240 -- noop
012625 -- mov (sp)+,(r5)+ ; save pirq level mask
000002 -- rti
#11200
#-----
wal 011200 -- data:
bwm 8
000000 -- mem(11200)=0 ; new pirq @ level 0
000000 -- mem(11202)=0 ; new pirq @ level 1
000000 -- mem(11204)=0 ; new pirq @ level 2
100000 -- mem(11206)=100000 ; new pirq @ level 3 -> 7
022000 -- mem(11210)=022000 ; new pirq @ level 4 -> 5+2
000000 -- mem(11212)=0 ; new pirq @ level 5
000000 -- mem(11214)=0 ; new pirq @ level 6
050000 -- mem(11216)=050000 ; new pirq @ level 7 -> 6+4
#
C Exec code 32 (PIRQ test)
#
wr3 177772 -- r3=177772 (#PIRQ)
wr4 177776 -- r4=177776 (#PSW)
wr5 011220 -- r1=11220 (output data)
wsp 001400 -- sp=1400
cres
stapc 011100 -- start @ 11100
wtgo
rr5 d=011300 -- ! r5
rsp d=001400 -- ! sp
rpc d=011134 -- ! pc
rps d=000000 -- ! PSW
wal 177772 --
rmi d=000000 -- ! PIRQ
wal 011220 --
brm 24
d=000340 -- ! mem(11220) PSW after SPL 7
d=001042 -- ! mem(11222) PIRQ when 1 set
d=005146 -- ! mem(11224) PIRQ when 1+3 set
d=001374 -- ! mem(11226) -> PI:3 SP
d=005146 -- ! mem(11230) PIRQ (3+1 pending)
d=001366 -- ! mem(11232) -> PI:7 SP
d=101356 -- ! mem(11234) PIRQ (7+1 pending)
d=100000 -- ! mem(11236) <- PI:7 mask
d=001366 -- ! mem(11240) -> PI:6 SP
d=051314 -- ! mem(11242) PIRQ (6+4+1 pending)
d=040000 -- ! mem(11244) <- PI:6 mask
d=001366 -- ! mem(11246) -> PI:4 SP
d=011210 -- ! mem(11250) PIRQ (4+1 pending)
d=001360 -- ! mem(11252) -> PI:5 SP
d=023252 -- ! mem(11254) PIRQ (5+2+1 pending)
d=020000 -- ! mem(11256) <- PI:5 mask
d=010000 -- ! mem(11260) <- PI:4 mask
d=004000 -- ! mem(11262) <- PI:3 mask
d=001374 -- ! mem(11264) -> PI:2 SP
d=003104 -- ! mem(11266) PIRQ
d=002000 -- ! mem(11270) <- PI:2 mask
d=001374 -- ! mem(11272) -> PI:1 SP
d=001042 -- ! mem(11274) PIRQ
d=001000 -- ! mem(11276) <- PI:1 mask
#
wal 000240 -- vector: 240 -> trap catcher again
bwm 2
000242 -- PC:242
000000 -- PS:0
#-----------------------------------------------------------------------------
C Setup code 33 [base 11200; use 112-113] (adc(b) and sbc(b) test)
#
wal 011200 -- code test 1: (adc)
bwm 5
006020 -- L1: ror (r0)+
005520 -- adc (r0)+
006120 -- rol (r0)+
077104 -- sob r1,L1 (.-4)
000000 -- halt
#-----
wal 011220 -- code test 2: (sbc)
bwm 5
006020 -- L1: ror (r0)+
005620 -- sbc (r0)+
006120 -- rol (r0)+
077104 -- sob r1,L1 (.-4)
000000 -- halt
#-----
wal 011240 -- code test 3: (adcb)
bwm 5
006020 -- L1: ror (r0)+
105520 -- adcb (r0)+
106120 -- rolb (r0)+
077104 -- sob r1,L1 (.-4)
000000 -- halt
#-----
wal 011260 -- code test 4: (sbcb)
bwm 5
006020 -- L1: ror (r0)+
105620 -- sbcb (r0)+
106120 -- rolb (r0)+
077104 -- sob r1,L1 (.-4)
000000 -- halt
#-----
wal 011300 -- data test 1: (adc)
bwm 9
000000 -- 177776 + 0 -> 177776 + 0
177776
000000
000001 -- 177776 + 1 -> 177777 + 0
177776
000000
000001 -- 177777 + 1 -> 000000 + 1
177777
000000
#-----
wal 011324 -- data test 2: (sbc)
bwm 9
000000 -- 000002 - 0 -> 000002 - 0
000002
000000
000001 -- 000002 - 1 -> 000001 - 0
000002
000000
000001 -- 000000 - 1 -> 177777 - 1
000000
000000
#-----
wal 011350 -- data test 3: (adcb)
bwm 6
000000 -- 376 + 0 -> 376 + 0
000376
000001 -- 376 + 1 -> 377 + 0
000376
000001 -- 377 + 1 -> 000 + 1
000377
#-----
wal 011364 -- data test 4: (sbcb)
bwm 6
000000 -- 002 - 0 -> 002 - 0
000002
000001 -- 002 - 1 -> 001 - 0
000002
000001 -- 000 - 1 -> 337 - 1
000000
#
C Exec code 33 (adc and sbc test)
C Exec test 33.1 (adc)
#
wr0 011300 -- r0=11300
wr1 000003 -- r1=3
wsp 001400 -- sp=1400
cres
stapc 011200 -- start @ 11200
wtgo
rr0 d=011322 -- ! r0=11322
rpc d=011212 -- ! pc
wal 011300
brm 9
d=000000 -- ! mem(11300)=000000 -- 177776 + 0 -> 177776 + 0
d=177776 -- ! mem(11302)=000000
d=000000 -- ! mem(11304)=000000
d=000000 -- ! mem(11306)=000000 -- 177776 + 1 -> 177777 + 0
d=177777 -- ! mem(11310)=000000
d=000000 -- ! mem(11312)=000000
d=000000 -- ! mem(11314)=000000 -- 177777 + 1 -> 000000 + 1
d=000000 -- ! mem(11316)=000000
d=000001 -- ! mem(11320)=000000
#----
C Exec test 33.2 (sbc)
#
wr0 011324 -- r0=11324
wr1 000003 -- r1=3
wsp 001400 -- sp=1400
cres
stapc 011220 -- start @ 11220
wtgo
rr0 d=011346 -- ! r0=11346
rpc d=011232 -- ! pc
wal 011324
brm 9
d=000000 -- ! mem(11324)=000000 -- 000002 - 0 -> 000002 - 0
d=000002 -- ! mem(11326)=000000
d=000000 -- ! mem(11330)=000000
d=000000 -- ! mem(11332)=000000 -- 000002 - 1 -> 000001 - 0
d=000001 -- ! mem(11334)=000000
d=000000 -- ! mem(11336)=000000
d=000000 -- ! mem(11340)=000000 -- 000000 - 1 -> 177777 - 1
d=177777 -- ! mem(11342)=000000
d=000001 -- ! mem(11344)=000000
#----
C Exec test 33.3 (adcb)
#
wr0 011350 -- r0=11350
wr1 000003 -- r1=3
wsp 001400 -- sp=1400
cres
stapc 011240 -- start @ 11240
wtgo
rr0 d=011364 -- ! r0=11364
rpc d=011252 -- ! pc
wal 011350
brm 6
d=000000 -- ! mem(11350)=000000 -- 376 + 0 -> 376 + 0
d=000376 -- ! mem(11352)=000000
d=000000 -- ! mem(11354)=000000 -- 376 + 1 -> 377 + 0
d=000377 -- ! mem(11356)=000000
d=000000 -- ! mem(11360)=000000 -- 377 + 1 -> 000 + 1
d=000400 -- ! mem(11362)=000000
#----
C Exec test 33.4 (sbcb)
#
wr0 011364 -- r0=11364
wr1 000003 -- r1=3
wsp 001400 -- sp=1400
cres
stapc 011260 -- start @ 11260
wtgo
rr0 d=011400 -- ! r0=11400
rpc d=011272 -- ! pc
wal 011364
brm 6
d=000000 -- ! mem(11364)=000000 -- 002 - 0 -> 002 - 0
d=000002 -- ! mem(11366)=000000
d=000000 -- ! mem(11370)=000000 -- 002 - 1 -> 001 - 0
d=000001 -- ! mem(11372)=000000
d=000000 -- ! mem(11374)=000000 -- 000 - 1 -> 337 - 1
d=000777 -- ! mem(11377)=000000
#-----------------------------------------------------------------------------
C Setup code 34 [base 11400; use 114-115] (11/34 self test code)
# code adapted from M9312 23-248F1 console PROM, the 11/04-34 Diagnostic PROM
#
wal 011400 -- code:
bwm 51
005000 -- clr r0 ; r0=000000 c=0
005200 -- inc r0 ; r0=000001 c=0
005100 -- com r0 ; r0=177776 c=1
006200 -- asr r0 ; r0=177777 c=0
006300 -- asl r0 ; r0=177776 c=1
006000 -- ror r0 ; r0=177777 c=0
005700 -- tst r0 ; r0=177777 c=0 ?impact unclear?
005400 -- neg r0 ; r0=000001 c=1
#11420
005300 -- dec r0 ; r0=000000 c=1
005600 -- sbc r0 ; r0=177777 c=1
006100 -- rol r0 ; r0=177777 c=1
005500 -- adc r0 ; r0=000000 c=1
000300 -- swab r0 ; r0=000000 c=0
001401 -- beq .+1 ;
000000 -- halt ;
012702 -- mov #data0,r2 ; r2=011560
#11440
011560
011203 -- mov (r2),r3 ; r2=011560 r3=011560
022203 -- cmp (r2)+,r3 ; r2=011562 r3=011560
001401 -- beq .+1 ;
000000 -- halt ;
063203 -- add @(r2)+,r3 ; r2=011564 r3=<2*11560>
165203 -- sub @-(r2),r3 ; r2=011562 r3=011560
044203 -- bic -(r2),r3 ; r2=011560 r3=000000
#11460
056203 -- bis 12(r2),r3 ; r2=011560 r3=011566
000012
037203 -- bis @12(r2),r3 ; r2=011560 r3=011566
000012
001001 -- bne .+1 ;
000000 -- halt ;
010701 -- mov pc,r1 ; r1=011476
000121 -- jmp (r1)+ ; jump 1.self 2. next; r1=011500
#11500
012701 -- mov #L2,r1 ; r1=011510
011510
000131 -- jmp @(r1)+ ; r1=011512 pc=011506
000111 -- L1:jmp (r1) ; r1=011512 pc=011512
011506 -- L2:.word L1
105737 -- tstb data1 ;
011564
001401 -- beq .+1 ;
#11520
000000 -- halt ;
010204 -- mov r2,r4 ; keep r2 for later check
022424 -- cmp (r4)+,(r4)+ ; r4=011564
105724 -- tstb (r4)+ ; r4=011565 (r4)+=000
001401 -- beq .+1 ;
000000 -- halt ;
105714 -- tstb (r4) ; r4=011565 (r4)=200
100402 -- bmi .+2 ;
#11540
000000 -- halt ;
000000 -- halt ;
000000 -- halt ;
#-----
wal 011560 -- data:
bwm 8
011560 -- data0: .word data0
011560 -- .word data0
100000 -- data1: .byte 000,200
177777 -- data2: .word 177777
011566 -- .word data2
011566 -- .word data2
000700 -- .word mem+0
000701 -- .word mem+1
#
C Exec code 34 (11/34 self test code)
# D RE RQ FU DAT
cres
stapc 011400 -- start @ 11400
wtgo
rr0 d=000000 -- ! r0
rr1 d=011512 -- ! r1
rr2 d=011560 -- ! r2
rr3 d=011566 -- ! r3
rr4 d=011565 -- ! r4
rpc d=011546 -- ! pc
#-----------------------------------------------------------------------------
C Setup code 35 [base 11600; use 116-121] (11/70 self test code)
# code adapted from M9312 23-616F1 console PROM, the 11/60-70 Diagnostic PROM
#
wal 011600 -- code:
bwm 117
005006 -- clr sp ; sp=000000
100404 -- bmi L3 ;
102403 -- bvs L3 ;
101002 -- bhi L3 ;
002401 -- blt L3 ;
101401 -- blos L4 ;
000000 -- L3: halt ;
005306 -- L3: dec sp ; sp=177777
#11620
100003 -- bpl L5 ;
001402 -- beq L5 ;
002001 -- bge L5 ;
003401 -- ble L6 ;
000000 -- L5: halt ;
006006 -- L6: ror sp ; sp=077777
102002 -- bvc L7 ;
103001 -- bcc L7 ;
#11640
001001 -- bne L8 ;
000000 -- L7: halt ;
012706 -- L8: mov #125252,sp ; sp=125252
125252
010600 -- mov sp,r0 ;
010001 -- mov r0,r1 ;
010102 -- mov r1,r2 ;
010203 -- mov r2,r3 ;
#11660
010304 -- mov r3,r4 ;
010405 -- mov r4,r5 ;
160501 -- sub r5,r1 ; r1=00000
002401 -- blt L9a ;
001401 -- beq L9 ;
000000 -- L9a: halt ;
006102 -- L9: rol r2 ; r2=052524 c=1
103001 -- bcc L10 ;
#11700
002401 -- blt L11 ;
000000 -- L10: halt ;
060203 -- L11: add r2,r3 ; r3=177776 (125252+052524)
005203 -- inc r3 ; r3=177777
005103 -- com r3 ; r3=000000
060301 -- add r3,r1 ; r1=000000 c=0
103401 -- bcs L12 ;
003401 -- ble L13 ;
#11720
000000 -- L12: halt ;
006004 -- L13: ror r4 ; r4=052525
050403 -- bis r4,r3 ; r3=052525 (r3 was 0)
060503 -- add r5,r3 ; r3=177777 c=0 (125252+052525)
005203 -- inc r3 ; r3=000000 c=0 (kept)
103402 -- bcs L14 ;
005301 -- dec r1 ; r1=177777
002401 -- blt L15 ;
#11740
000000 -- L14: halt ;
005100 -- L15: com r0 ; r0=052525
101401 -- blos L16 ;
000000 -- halt ;
040001 -- L16: bic r0,r1 ; r1=125252
060101 -- L16: add r1,r1 ; r1=052524 c=1
003001 -- bgt L17 ;
003401 -- ble L18 ;
#11760
000000 -- L17: halt ;
000301 -- L18: swab r1 ; r1=052125
020127 -- cmp r1,#052125 ;
052125
001004 -- bne L19 ;
030405 -- bit r4,r5 ;
003002 -- bgt L19 ;
005105 -- com r5 ; r5=052525
#12000
001001 -- bne L20 ;
000000 -- L19: halt ;
112700 -- L20: movb #177401,r0 ;
177401
100001 -- bpl L21 ;
000000 -- L22: halt ;
077002 -- L21: sob r0,L22 ;
000261 -- sec ; c=1
#12020
006100 -- rol r0 ; r0=000001
006100 -- rol r0 ; r0=000002
006100 -- rol r0 ; r0=000004
010001 -- mov r0,r1 ; r1=000004
005401 -- neg r1 ; r1=177774
005201 -- L23: inc r1 ;
077002 -- sob r0,L23 ;
005700 -- tst r0 ; here r0=r1=0
#12040
001002 -- bne L24 ;
005701 -- tst r1 ;
001401 -- beq L25 ;
000000 -- L24: halt ;
012706 -- L25: mov #776,sp ;
000776 --
004767 -- jsr pc,L26 ;
000002
#12060
000000 -- N2: halt ;
022716 -- L26: cmp #N2,(sp) ;
012060
001401 -- beq L27 ;
000000 -- halt ;
012716 -- L27: mov #N3,(sp) ;
012102
000207 -- rts pc ;
#12100
000000 -- halt ;
005046 -- N3: clr -(sp) ;
012746 -- mov #N4,-(sp) ;
012114
000002 -- rti ;
000000 -- halt ;
000137 -- N4: jmp @#N5 ;
012122
#12120
000000 -- halt ;
012705 -- N5: mov #160000,r5 ; r5=160000
160000
005037 -- clr @#6 ;
000006
012737 -- mov #N6,@#4 ;
012150
000004
#12140
012706 -- mov #776,sp ; sp=776
000776
005715 -- tst (r5) ; will fail, first word of I/O page
000000 -- halt ;
000000 -- N6: halt ;
#
C Exec code 35 (11/70 self test code)
# D RE RQ FU DAT
cres
stapc 011600 -- start @ 11600
wtgo
rpc d=012152 -- ! pc
wal 000004 -- vector: 4 -> trap catcher again
bwm 2
000006 -- PC:6
000000 -- PS:0
#-----------------------------------------------------------------------------
# Up to here code and data (both input and result) occupied 'fresh' memory.
# Easy to debug, but inconvenient when test should be extended later.
# From here on, only code will always occupy fresh memory.
# Data will be put into the upper part of the 16 kbyte memory:
# test vector: 036000 (512 byte area)
# result data: 037000 (512 byte area)
#-----------------------------------------------------------------------------
C Setup code 36 [base 12200] (systematic CMP test)
#
wal 012200 -- code:
bwm 7
000230 -- spl 0
012400 -- L1: mov (r4)+,r0
012401 -- mov (r4)+,r1
020001 -- cmp r0,r1
011225 -- mov (r2),(r5)+
077305 -- sob r3,L1
000000 -- halt
#
C Exec code 36 (systematic CMP test)
C Exec test 36.1: data adapted from cmp.s11 code of Begemot p11-2.10c
#
wal 036000 -- setup test vector:
bwm 22
000000 -- 000000, 000000 --> nzvc=0100
000000 --
000001 -- 000001, 000001 --> nzvc=0100
000001 --
177777 -- 177777, 177777 --> nzvc=0100
177777 --
000000 -- 000000, 000001 --> nzvc=1001
000001 --
000000 -- 000000, 177777 --> nzvc=0001
177777 --
000001 -- 000001, 000000 --> nzvc=0000
000000 --
177777 -- 177777, 000000 --> nzvc=1000
000000 --
000001 -- 000001, 177777 --> nzvc=0001
177777 --
177777 -- 177777, 000001 --> nzvc=1000
000001 --
077777 -- 077777, 100000 --> nzvc=1011
100000 --
100000 -- 100000, 077777 --> nzvc=0010
077777 --
#----
wr2 177776 -- r2=177776 -> psw
wr3 000013 -- r3=13 -> test count
wr4 036000 -- r4=36000 -> input area
wr5 037000 -- r5=37000 -> output area
wsp 001400 -- sp=1400
cres
stapc 012200 -- start @ 12200
wtgo
rpc d=012216 -- ! pc
rr3 d=000000 -- ! r3=0
rr4 d=036054 -- ! r4=12354
rr5 d=037026 -- ! r5=12426
wal 037000 --
brm 11
d=000004 -- 000000, 000000 --> nzvc=0100
d=000004 -- 000001, 000001 --> nzvc=0100
d=000004 -- 177777, 177777 --> nzvc=0100
d=000011 -- 000000, 000001 --> nzvc=1001
d=000001 -- 000000, 177777 --> nzvc=0001
d=000000 -- 000001, 000000 --> nzvc=0000
d=000010 -- 177777, 000000 --> nzvc=1000
d=000001 -- 000001, 177777 --> nzvc=0001
d=000010 -- 177777, 000001 --> nzvc=1000
d=000013 -- 077777, 100000 --> nzvc=1011
d=000002 -- 100000, 077777 --> nzvc=0010
#-----------------------------------------------------------------------------
C Setup code 37 [base 12300] (systematic DIV test)
#
wal 012300 -- code:
bwm 9
000230 -- spl 0
012400 -- L1: mov (r4)+,r0
012401 -- mov (r4)+,r1
071024 -- div (r4)+,r0
011225 -- mov (r2),(r5)+
010025 -- mov r0,(r5)+
010125 -- mov r1,(r5)+
077307 -- sob r3,L1
#12520
000000 -- halt
#
C Exec code 37 (systematic DIV test)
C Exec test 37.1: data adapted from div.s11 code of Begemot p11-2.10c
#
wal 036000 -- setup test vector:
bwm 57
000000 -- 0, 4, 0, 7, 0, 4# 4/ 0 -> 0111 0 4
000004 --
000000 --
000000 -- 0, 4, 2, 0, 2, 0# 4/ 2 -> 0000 2 0
000004 --
000002 --
000000 -- 0, 6, 2, 0, 3, 0# 6/ 2 -> 0000 3 0
000006 --
000002 --
000000 -- 0, 4, -2, 10, -2, 0# 4/-2 ->1000 -2 0
000004 --
177776 --
#36030
000002 -- 2, 0, 1, 2, 2, 0# 0x20000 / 1
000000 --
000001 --
000002 -- 2, 0, -2, 12, 2, 0# 0x20000 / -2
000000 --
177776 --
100000 -- 100000, 0, 1, 12,100000, 0# 0x80000000 / 1
000000 --
000001 --
177776 -- 177776,177777, -1, 2,177776,177777# -0x10001 / -1
177777 --
177777 --
#36060
177777 -- 177777,177773, 2, 10, -2, -1# -5 / 2
177773 --
000002 --
177777 -- 177777,177773, -2, 0, 2, -1# -5 / -2
177773 --
177776 --
177776 -- 177776, 0, 40000, 10, -10, 0# -0x20000/0x4000
000000 --
040000 --
000100 -- 100, 200,177601, 12, 100, 200# 0x400080 / -0x7f
000200 --
177601 --
#36110
000000 -- 0, 1, 0, 7, 0, 1 # zero divide
000001 --
000000 --
177777 -- -1, -1, 0, 7, -1, -1 # zero divide
177777 --
000000 --
000000 -- 0, 0, 0, 7, 0, 0 # zero divide
000000 --
000000 --
000001 -- 1, 1, 1, 2, 1, 1 # overflow
000001 --
000001 --
#36140
000001 -- 1, 1, -1, 012, 1, 1 # overflow
000001 --
177777 --
177777 -- -1, -1, 1, 010, -1, 0 # wfjm corrected, not overflow
177777 --
000001 --
177777 -- -1, -1, -1, 0, 1, 0 # wfjm corrected, not overflow
177777 --
177777 --
#----
wr2 177776 -- r2=177776 -> psw
wr3 000023 -- r3=23 -> test count
wr4 036000 -- r4=36000 -> input area
wr5 037000 -- r5=37000 -> output area
wsp 001400 -- sp=1400
cres
stapc 012300 -- start @ 12300
wtgo
rpc d=012322 -- ! pc
rr3 d=000000 -- ! r3=0
rr4 d=036162 -- ! r4=36162
rr5 d=037162 -- ! r5=37162
wal 037000 --
brm 57
d=000007 --! 0, 4, 0, 7, 0, 4# 4/ 0 -> 0111 0 4
d=000000 --!
d=000004 --!
d=000000 --! 0, 4, 2, 0, 2, 0# 4/ 2 -> 0000 2 0
d=000002 --!
d=000000 --!
d=000000 --! 0, 6, 2, 0, 3, 0# 6/ 2 -> 0000 3 0
d=000003 --!
d=000000 --!
d=000010 --! 0, 4, -2, 10, -2, 0# 4/-2 ->1000 -2 0
d=177776 --!
d=000000 --!
#37030
d=000002 --! 2, 0, 1, 2, 2, 0# 0x20000 / 1
d=000002 --!
d=000000 --!
d=000012 --! 2, 0, -2, 12, 2, 0# 0x20000 / -2
d=000002 --!
d=000000 --!
d=000012 --!100000, 0, 1, 12,100000, 0# 0x80000000 / 1
d=100000 --!
d=000000 --!
d=000002 --!177776,177777, -1, 2,177776,177777# -0x10001 / -1
d=177776 --!
d=177777 --!
#37060
d=000010 --!177777,177773, 2, 10, -2, -1# -5 / 2
d=177776 --!
d=177777 --!
d=000000 --!177777,177773, -2, 0, 2, -1# -5 / -2
d=000002 --!
d=177777 --!
d=000010 --!177776, 0, 40000, 10, -10, 0# -0x20000/0x4000
d=177770 --!
d=000000 --!
d=000012 --! 100, 200,177601, 12, 100, 200# 0x400080 / -0x7f
d=000100 --!
d=000200 --!
#37110
d=000007 --! 0, 1, 0, 7, 0, 1 # zero divide
d=000000 --!
d=000001 --!
d=000007 --! -1, -1, 0, 7, -1, -1 # zero divide
d=177777 --!
d=177777 --!
d=000007 --! 0, 0, 0, 7, 0, 0 # zero divide
d=000000 --!
d=000000 --!
d=000002 --! 1, 1, 1, 2, 1, 1 # overflow
d=000001 --!
d=000001 --!
#13740
d=000012 --! 1, 1, -1, 012, 1, 1 # overflow
d=000001 --!
d=000001 --!
d=000010 --! -1, -1, 1, 010, -1, 0 # wfjm corrected, not overflow
d=177777 --!
d=000000 --!
d=000000 --! -1, -1, -1, 0, 1, 0 # wfjm corrected, not overflow
d=000001 --!
d=000000 --!
#--------
C Exec test 37.2: data adapted from KDJ11.MAC, test 213, p. 139-141
# D RE RQ FU DAT
wal 036000 -- setup test vector:
bwm 51
177777 -- 177777,177777,177777, 0, 1, 0#
177777 --
177777 --
000000 -- 0,177777,177777,12, 0,177777# w11a:12,000001,000000
177777 --
177777 --
177777 -- 177777, 0,177777, 2,177777, 0#
000000 --
177777 --
000000 -- 0, 7642, 7643, 4, 0, 7642#
007642 --
007643 --
000000 -- 0, 137,177543, 4, 0, 137#
000137 --
177543 --
000000 -- 0, 7643, 7643, 0, 1, 0#
007643 --
007643 --
100000 -- 100000, 4376, 10021,12,100000, 4376#
004376 --
010021 --
177700 -- 177700,170033, 10021,10,176024,171307#
170033 --
010021 --
177700 -- 177700,170033,167757, 0, 1754,171307#
170033 --
167757 --
000000 -- 0,177777, 1, 2, 0,177777#
177777 --
000001 --
177777 -- 177777, 45716, 1,12,177777, 45716# w11a:12,045716,000000
045716 --
000001 --
000000 -- 0, 2,177770, 4, 0, 2#
000002 --
177770 --
177777 -- 177777,177776, 10, 4, 0,177776#
177776 --
000010 --
000001 -- 1,177777, 1, 2, 1,177777#
177777 --
000001 --
000001 -- 1, 0, 2, 2, 1, 0#
000000 --
000002 --
000001 -- 1, 0, 3, 0, 52525, 1#
000000 --
000003 --
000023 -- 23, 16054, 16537, 0, 246, 10222#
016054 --
016537 --
#----
wr2 177776 -- r2=177776 -> psw
wr3 000021 -- r3=21 (17.) -> test count
wr4 036000 -- r4=36000 -> input area
wr5 037000 -- r5=37000 -> output area
wsp 001400 -- sp=1400
cres
stapc 012300 -- start @ 12300
wtgo
rpc d=012322 -- ! pc
rr3 d=000000 -- ! r3=0
rr4 d=036146 -- ! r4=36146
rr5 d=037146 -- ! r5=37146
wal 037000 --
brm 51
d=000000 --!177777,177777,177777, 0, 1, 0#
d=000001 --!
d=000000 --!
d=000012 --! 0,177777,177777,12, 0,177777# w11a:12,000001,000000
d=000001 --!
d=000000 --!
d=000002 --!177777, 0,177777, 2,177777, 0#
d=177777 --!
d=000000 --!
d=000004 --! 0, 7642, 7643, 4, 0, 7642#
d=000000 --!
d=007642 --!
d=000004 --! 0, 137,177543, 4, 0, 137#
d=000000 --!
d=000137 --!
d=000000 --! 0, 7643, 7643, 0, 1, 0#
d=000001 --!
d=000000 --!
d=000012 --!100000, 4376, 10021,12,100000, 4376#
d=100000 --!
d=004376 --!
d=000010 --!177700,170033, 10021,10,176024,171307#
d=176024 --!
d=171307 --!
d=000000 --!177700,170033,167757, 0, 1754,171307#
d=001754 --!
d=171307 --!
d=000002 --! 0,177777, 1, 2, 0,177777#
d=000000 --!
d=177777 --!
d=000012 --!177777, 45716, 1,12,177777, 45716# w11a:12,045716,000000
d=045716 --!
d=000000 --!
d=000004 --! 0, 2,177770, 4, 0, 2#
d=000000 --!
d=000002 --!
d=000004 --!177777,177776, 10, 4, 0,177776#
d=000000 --!
d=177776 --!
d=000002 --! 1,177777, 1, 2, 1,177777#
d=000001 --!
d=177777 --!
d=000002 --! 1, 0, 2, 2, 1, 0#
d=000001 --!
d=000000 --!
d=000000 --! 1, 0, 3, 0, 52525, 1#
d=052525 --!
d=000001 --!
d=000000 --! 23, 16054, 16537, 0, 246, 10222#
d=000246 --!
d=010222 --!
#-----------------------------------------------------------------------------
C Setup code 40 [base 12400] (systematic ASH test)
#
wal 012400 -- code:
bwm 15
000230 -- spl 0
016400 -- L1: mov 2(r4),r0
000002
011412 -- mov (r4),(r2)
072064 -- ash 4(r4),r0
000004
011265 -- mov (r2),2(r5)
000002
#12420
010015 -- mov r0,(r5)
062704 -- add #6,r4
000006
062705 -- add #4,r5
000004
077315 -- sob r3,L1
000000 -- halt
#
C Exec code 40 (systematic ASH test)
C Exec test 40.1: data adapted from ash.s11 code of Begemot p11-2.10c
#
# The {} comments are original comments from Harti Brandt
# Annotations starting with !! indicated mods for W11
# Note, that the W11 does not have the microcode bugs of the J11 !
#
wal 036000 -- setup test vector:
# test shift amount 0
bwm 150
000000 -- 00, 000000, 000000, 000000, 04
000000 --
000000 --
000017 -- 17, 000000, 000000, 000000, 04
000000 --
000000 --
000017 -- 17, 100001, 000000, 100001, 10
100001 --
000000 --
000017 -- 17, 040001, 000000, 040001, 00
040001 --
000000 --
000017 -- 17, 040001, 177700, 040001, 00
040001 --
177700 --
# right shift positive values
000000 -- 00, 000000, 000077, 000000, 04
000000 --
000077 --
000017 -- 17, 000000, 000077, 000000, 04
000000 --
000077 --
000000 -- 00, 000002, 000077, 000001, 00
000002 --
000077 --
000000 -- 00, 000001, 000077, 000000, 05
000001 --
000077 --
000000 -- 00, 000003, 000076, 000000, 05
000003 --
000076 --
000000 -- 00, 000001, 000076, 000000, 04
000001 --
000076 --
000000 -- 00, 040000, 000062, 000001, 00
040000 --
000062 --
000000 -- 00, 040000, 000061, 000000, 05
040000 --
000061 --
000000 -- 00, 040000, 000060, 000000, 04
040000 --
000060 --
000000 -- 00, 040000, 000042, 000000, 04
040000 --
000042 --
000000 -- 00, 040000, 000041, 000000, 04
040000 --
000041 --
000000 -- 00, 040000, 000040, 000000, 04
040000 --
000040 --
000000 -- 00, 040000, 100037, 000000, 04
040000 --
100037 --
# right shift negative numbers
000000 -- 00, 100002, 000077, 140001, 10
100002 --
000077 --
000000 -- 00, 100002, 000076, 160000, 11
100002 --
000076 --
000000 -- 00, 100002, 000075, 170000, 10
100002 --
000075 --
000000 -- 00, 100002, 000062, 177776, 10
100002 --
000062 --
000000 -- 00, 100002, 000061, 177777, 10
100002 --
000061 --
000000 -- 00, 100002, 000060, 177777, 11
100002 --
000060 --
000000 -- 00, 100002, 000057, 177777, 11
100002 --
000057 --
000000 -- 00, 100002, 000056, 177777, 11
100002 --
000056 --
000000 -- 00, 100002, 000041, 177777, 11
100002 --
000041 --
000000 -- 00, 100002, 000040, 177777, 11
100002 --
000040 --
000000 -- 00, 100002, 040037, 177777, 11
100002 --
040037 --
# left shift positive numbers
000000 -- 00, 000000, 000001, 000000, 04
000000 --
000001 --
000017 -- 17, 000000, 000001, 000000, 04
000000 --
000001 --
000000 -- 00, 000001, 000007, 000200, 00
000001 --
000007 --
000000 -- 00, 000001, 000016, 040000, 00
000001 --
000016 --
000000 -- 00, 000001, 000017, 100000, 12
000001 --
000017 --
000000 -- 00, 000001, 000020, 000000, 07
000001 --
000020 --
000000 -- 00, 000001, 000021, 000000, 06
000001 --
000021 --
000000 -- 00, 000001, 000036, 000000, 06
000001 --
000036 --
000000 -- 00, 000001, 000037, 000000, 04 {????}
000001 --
000037 --
000000 -- 00, 000001, 000040, 000000, 04 {right shift!}
000001 --
000040 --
000000 -- 00, 000001, 010037, 000000, 04 {right shift!}
000001 --
010037 --
# left shift negative numbers
000000 -- 00, 100001, 000001, 000002, 03
100001 --
000001 --
000000 -- 00, 140001, 000001, 100002, 11
140001 --
000001 --
000000 -- 00, 140001, 000002, 000004, 03
140001 --
000002 --
000000 -- 00, 140001, 000016, 040000, 02
140001 --
000016 --
000000 -- 00, 140001, 000017, 100000, 12
140001 --
000017 --
000000 -- 00, 140001, 000020, 000000, 07
140001 --
000020 --
000000 -- 00, 140001, 000021, 000000, 06
140001 --
000021 --
000000 -- 00, 140002, 000035, 000000, 06
140002 --
000035 --
000000 -- 00, 140002, 000036, 000000, 06
140002 --
000036 --
000000 -- 00, 140002, 000037, 177777, 11 {????}
140002 --
000037 --
#----
wr2 177776 -- r2=177776 -> psw
wr3 000062 -- r3=62 -> test count
wr4 036000 -- r4=36000 -> input area
wr5 037000 -- r5=37000 -> output area
wsp 001400 -- sp=1400
cres
stapc 012400 -- start @ 12400
wtgo
rpc d=012436 -- ! pc
rr3 d=000000 -- ! r3=0
rr4 d=036454 -- ! r4=36454
rr5 d=037310 -- ! r5=37310
wal 037000 --
# test shift amount 0
brm 100
d=000000 -- 00, 000000, 000000, 000000, 04
d=000004 --
d=000000 -- 17, 000000, 000000, 000000, 04
d=000004 --
d=100001 -- 17, 100001, 000000, 100001, 10
d=000010 --
d=040001 -- 17, 040001, 000000, 040001, 00
d=000000 --
d=040001 -- 17, 040001, 177700, 040001, 00
d=000000 --
#37024 # right shift positive values
d=000000 -- 00, 000000, 000077, 000000, 04
d=000004 --
d=000000 -- 17, 000000, 000077, 000000, 04
d=000004 --
d=000001 -- 00, 000002, 000077, 000001, 00
d=000000 --
#37040
d=000000 -- 00, 000001, 000077, 000000, 05
d=000005 --
d=000000 -- 00, 000003, 000076, 000000, 05
d=000005 --
d=000000 -- 00, 000001, 000076, 000000, 04
d=000004 --
d=000001 -- 00, 040000, 000062, 000001, 00
d=000000 --
#37060
d=000000 -- 00, 040000, 000061, 000000, 05
d=000005 --
d=000000 -- 00, 040000, 000060, 000000, 04
d=000004 --
d=000000 -- 00, 040000, 000042, 000000, 04
d=000004 --
d=000000 -- 00, 040000, 000041, 000000, 04
d=000004 --
#37100
d=000000 -- 00, 040000, 000040, 000000, 04
d=000004 --
d=000000 -- 00, 040000, 100037, 000000, 04
d=000006 -- !!04->06
#37110 # right shift negative numbers
d=140001 -- 00, 100002, 000077, 140001, 10
d=000010 --
d=160000 -- 00, 100002, 000076, 160000, 11
d=000011 --
#37120
d=170000 -- 00, 100002, 000075, 170000, 10
d=000010 --
d=177776 -- 00, 100002, 000062, 177776, 10
d=000010 --
d=177777 -- 00, 100002, 000061, 177777, 10
d=000010 --
d=177777 -- 00, 100002, 000060, 177777, 11
d=000011 --
#37140
d=177777 -- 00, 100002, 000057, 177777, 11
d=000011 --
d=177777 -- 00, 100002, 000056, 177777, 11
d=000011 --
d=177777 -- 00, 100002, 000041, 177777, 11
d=000011 --
d=177777 -- 00, 100002, 000040, 177777, 11
d=000011 -- see Note below [[s:10]]
d=000000 -- 00, 100002, 040037, 177777, 11 !!-1->0
d=000006 -- !!11->06
#37164 # left shift positive numbers
d=000000 -- 00, 000000, 000001, 000000, 04
d=000004 --
d=000000 -- 17, 000000, 000001, 000000, 04
d=000004 --
d=000200 -- 00, 000001, 000007, 000200, 00
d=000000 --
#37200
d=040000 -- 00, 000001, 000016, 040000, 00
d=000000 --
d=100000 -- 00, 000001, 000017, 100000, 12
d=000012 --
d=000000 -- 00, 000001, 000020, 000000, 07
d=000007 --
d=000000 -- 00, 000001, 000021, 000000, 06
d=000006 --
#37220
d=000000 -- 00, 000001, 000036, 000000, 06
d=000006 --
d=000000 -- 00, 000001, 000037, 000000, 04 {????}
d=000006 -- !!04->06
d=000000 -- 00, 000001, 000040, 000000, 04 {right shift!}
d=000004 --
d=000000 -- 00, 000001, 010037, 000000, 04 {right shift!}
d=000006 -- !!04->06
#37240 # left shift negative numbers
d=000002 -- 00, 100001, 000001, 000002, 03
d=000003 --
d=100002 -- 00, 140001, 000001, 100002, 11
d=000011 --
d=000004 -- 00, 140001, 000002, 000004, 03
d=000003 --
d=040000 -- 00, 140001, 000016, 040000, 02
d=000002 --
#37260
d=100000 -- 00, 140001, 000017, 100000, 12
d=000012 --
d=000000 -- 00, 140001, 000020, 000000, 07
d=000007 --
d=000000 -- 00, 140001, 000021, 000000, 06
d=000006 --
d=000000 -- 00, 140002, 000035, 000000, 06
d=000006 --
#37300
d=000000 -- 00, 140002, 000036, 000000, 06
d=000006 --
d=000000 -- 00, 140002, 000037, 177777, 11 {????} !!-1->0
d=000006 -- !!11->06
#
# simh notes:
# 1. ash dst=100002,src=040 sets C=0 in simh. PSW is: s:10 b:11 W11:11
#
#-----------------------------------------------------------------------------
C Setup code 41 [base 12500] (systematic ASHC even test)
#
wal 012500 -- code:
bwm 19
000230 -- spl 0
016400 -- L1: mov 2(r4),r0
000002
016401 -- mov 4(r4),r1
000004
011412 -- mov (r4),(r2)
073064 -- ashc 6(r4),r0
000006
#12520
011265 -- mov (r2),4(r5)
000004
010015 -- mov r0,(r5)
010165 -- mov r1,2(r5)
000002
062704 -- add #10,r4
000010
062705 -- add #6,r5
#12540
000006
077321 -- sob r3,L1
000000 -- halt
#
C Exec code 41 (systematic ASHC even test)
C Exec test 41.1: data adapted from ashc.s11 code of Begemot p11-2.10c
#
# The {} comments are original comments from Harti Brandt
# Annotations starting with !! indicated mods for W11
# Note, that the W11 does not have the microcode bugs of the J11 !
#
wal 036000 -- setup test vector:
# test when no shift at all, cc must be correctly set
bwm 188
000000 -- 00, 000000, 000000, 000000, 000000, 000000, 04
000000 --
000000 --
000000 --
000017 -- 17, 000000, 000000, 000000, 000000, 000000, 04
000000 --
000000 --
000000 --
000017 -- 17, 040000, 000001, 000000, 040000, 000001, 00
040000 --
000001 --
000000 --
000017 -- 17, 100000, 000001, 000000, 100000, 000001, 10
100000 --
000001 --
000000 --
000017 -- 17, 100000, 000001, 177700, 100000, 000001, 10
100000 --
000001 --
177700 --
# right shifts of positive numbers
000000 -- 00, 000000, 000000, 000077, 000000, 000000, 04
000000 --
000000 --
000077 --
000017 -- 17, 000000, 000000, 000077, 000000, 000000, 04
000000 --
000000 --
000077 --
000000 -- 00, 040000, 000000, 000077, 020000, 000000, 00
040000 --
000000 --
000077 --
000000 -- 00, 040000, 000000, 177777, 020000, 000000, 00
040000 --
000000 --
000077 --
000000 -- 00, 040000, 000000, 000060, 000000, 040000, 00
040000 --
000000 --
000060 --
000000 -- 00, 040000, 000000, 000042, 000000, 000001, 00
040000 --
000000 --
000042 --
000000 -- 00, 040000, 000000, 000041, 000000, 000000, 05
040000 --
000000 --
000041 --
000000 -- 00, 040000, 000000, 000040, 000000, 000000, 04
040000 --
000000 --
000040 --
000000 -- 00, 040000, 000000, 177737, 000000, 000000, 04
040000 --
000000 --
177737 --
000000 -- 00, 000000, 000001, 177737, 000000, 000000, 04
000000 --
000001 --
177737 --
# right shifts of negative numbers
000000 -- 00, 100000, 000002, 000077, 140000, 000001, 10
100000 --
000002 --
000077 --
000000 -- 00, 100020, 000001, 000077, 140010, 000000, 11
100020 --
000001 --
000077 --
000000 -- 00, 177777, 177776, 000077, 177777, 177777, 10
177777 --
177776 --
000077 --
000000 -- 00, 177777, 177777, 000077, 177777, 177777, 11
177777 --
177777 --
000077 --
000000 -- 00, 100000, 100000, 000060, 177777, 100000, 11
100000 --
100000 --
000060 --
000000 -- 00, 100000, 000000, 000060, 177777, 100000, 10
100000 --
000000 --
000060 --
000000 -- 00, 100000, 000001, 000042, 177777, 177776, 10
100000 --
000001 --
000042 --
000000 -- 00, 100000, 000001, 000041, 177777, 177777, 10
100000 --
000001 --
000041 --
000000 -- 00, 100000, 000001, 000040, 177777, 177777, 11
100000 --
000001 --
000040 --
000000 -- 00, 100000, 000001, 177737, 177777, 177777, 11
100000 --
000001 --
177737 --
# left shifts of positive numbers
000000 -- 00, 000000, 000000, 000001, 000000, 000000, 04
000000 --
000000 --
000001 --
000017 -- 17, 000000, 000000, 000001, 000000, 000000, 04
000000 --
000000 --
000001 --
000000 -- 00, 000002, 000001, 000001, 000004, 000002, 00
000002 --
000001 --
000001 --
000000 -- 00, 000002, 100000, 000001, 000005, 000000, 00
000002 --
100000 --
000001 --
000000 -- 00, 040000, 000000, 000001, 100000, 000000, 12
040000 --
000000 --
000001 --
000000 -- 00, 040000, 000000, 000002, 000000, 000000, 07
040000 --
000000 --
000002 --
000000 -- 00, 040000, 000000, 000003, 000000, 000000, 06
040000 --
000000 --
000003 --
000000 -- 00, 000000, 000001, 177701, 000000, 000002, 00
000000 --
000001 --
177701 --
000000 -- 00, 000000, 000001, 177735, 020000, 000000, 00
000000 --
000001 --
177735 --
000000 -- 00, 000000, 000001, 177736, 040000, 000000, 00
000000 --
000001 --
177736 --
000000 -- 00, 000000, 000001, 000037, 100000, 000000, 12 {left shift!}
000000 --
000001 --
000037 --
000000 -- 00, 000000, 000001, 177737, 000000, 000000, 04 {right shift!}
000000 --
000001 --
177737 --
000000 -- 00, 000000, 000001, 020037, 000000, 000000, 04 {right shift!}
000000 --
000001 --
020037 --
# left shifts of negative numbers
000000 -- 00, 177777, 177777, 000001, 177777, 177776, 11
177777 --
177777 --
000001 --
000000 -- 00, 177777, 177777, 000002, 177777, 177774, 11
177777 --
177777 --
000002 --
000000 -- 00, 177777, 177777, 000036, 140000, 000000, 11
177777 --
177777 --
000036 --
000000 -- 00, 177777, 177777, 000037, 100000, 000000, 11
177777 --
177777 --
000037 --
000000 -- 00, 177777, 177776, 000037, 000000, 000000, 07
177777 --
177776 --
000037 --
000000 -- 00, 177777, 177774, 000037, 000000, 000000, 06
177777 --
177774 --
000037 --
000000 -- 00, 177777, 177777, 177701, 177777, 177776, 11
177777 --
177777 --
177701 --
000000 -- 00, 177777, 177777, 001037, 177777, 177777, 11 {right shift!}
177777 --
177777 --
001037 --
000000 -- 00, 177777, 177777, 001036, 140000, 000000, 11
177777 --
177777 --
001036 --
#----
wr2 177776 -- r2=177776
wr3 000057 -- r3=57 (47.)
wr4 036000 -- r4=36000
wr5 037000 -- r5=37000
wsp 001400 -- sp=1400
cres
stapc 012500 -- start @ 12500
wtgo
rpc d=012546 -- ! pc
rr3 d=000000 -- ! r3=0
rr4 d=036570 -- ! r4=36570
rr5 d=037432 -- ! r5=37432
wal 037000 --
# test when no shift at all, cc must be correctly set
brm 141
d=000000 --!00, 000000, 000000, 000000, 000000, 000000, 04
d=000000 --!
d=000004 --!
d=000000 --!17, 000000, 000000, 000000, 000000, 000000, 04
d=000000 --!
d=000004 --!
d=040000 --!17, 040000, 000001, 000000, 040000, 000001, 00
d=000001 --!
d=000000 --!
d=100000 --!17, 100000, 000001, 000000, 100000, 000001, 10
d=000001 --!
d=000010 --!
#37030
d=100000 --!17, 100000, 000001, 177700, 100000, 000001, 10
d=000001 --!
d=000010 --!
# right shifts of positive numbers
d=000000 --!00, 000000, 000000, 000077, 000000, 000000, 04
d=000000 --!
d=000004 --!
d=000000 --!17, 000000, 000000, 000077, 000000, 000000, 04
d=000000 --!
d=000004 --!
d=020000 --!00, 040000, 000000, 000077, 020000, 000000, 00
d=000000 --!
d=000000 --!
#37060
d=020000 --!00, 040000, 000000, 177777, 020000, 000000, 00
d=000000 --!
d=000000 --!
d=000000 --!00, 040000, 000000, 000060, 000000, 040000, 00
d=040000 --!
d=000000 --!
d=000000 --!00, 040000, 000000, 000042, 000000, 000001, 00
d=000001 --!
d=000000 --!
d=000000 --!00, 040000, 000000, 000041, 000000, 000000, 05
d=000000 --!
d=000005 --!
#37110
d=000000 --!00, 040000, 000000, 000040, 000000, 000000, 04
d=000000 --!
d=000004 --!
d=000000 --!00, 040000, 000000, 177737, 000000, 000000, 04
d=000000 --!
d=000006 --! !!04->06
d=100000 --!00, 000000, 000001, 177737, 000000, 000000, 04!!->100000
d=000000 --!
d=000012 --! !!04->12
# right shifts of negative numbers
d=140000 --!00, 100000, 000002, 000077, 140000, 000001, 10
d=000001 --!
d=000010 --!
#37140
d=140010 --!00, 100020, 000001, 000077, 140010, 000000, 11
d=000000 --!
d=000011 --!
d=177777 --!00, 177777, 177776, 000077, 177777, 177777, 10
d=177777 --!
d=000010 --!
d=177777 --!00, 177777, 177777, 000077, 177777, 177777, 11
d=177777 --!
d=000011 --!
d=177777 --!00, 100000, 100000, 000060, 177777, 100000, 11
d=100000 --!
d=000011 --!
#37170
d=177777 --!00, 100000, 000000, 000060, 177777, 100000, 10
d=100000 --!
d=000010 --!
d=177777 --!00, 100000, 000001, 000042, 177777, 177776, 10
d=177776 --!
d=000010 --!
d=177777 --!00, 100000, 000001, 000041, 177777, 177777, 10
d=177777 --!
d=000010 --!
d=177777 --!00, 100000, 000001, 000040, 177777, 177777, 11
d=177777 --!
d=000011 --!
#37220
d=100000 --!00, 100000, 000001, 177737, 177777, 177777, 11!!->100000
d=000000 --! !!->000000
d=000012 --! !!11->12
# left shifts of positive numbers
d=000000 --!00, 000000, 000000, 000001, 000000, 000000, 04
d=000000 --!
d=000004 --!
d=000000 --!17, 000000, 000000, 000001, 000000, 000000, 04
d=000000 --!
d=000004 --!
d=000004 --!00, 000002, 000001, 000001, 000004, 000002, 00
d=000002 --!
d=000000 --!
#37250
d=000005 --!00, 000002, 100000, 000001, 000005, 000000, 00
d=000000 --!
d=000000 --!
d=100000 --!00, 040000, 000000, 000001, 100000, 000000, 12
d=000000 --!
d=000012 --!
d=000000 --!00, 040000, 000000, 000002, 000000, 000000, 07
d=000000 --!
d=000007 --!
d=000000 --!00, 040000, 000000, 000003, 000000, 000000, 06
d=000000 --!
d=000006 --!
#37300
d=000000 --!00, 000000, 000001, 177701, 000000, 000002, 00
d=000002 --!
d=000000 --!
d=020000 --!00, 000000, 000001, 177735, 020000, 000000, 00
d=000000 --!
d=000000 --!
d=040000 --!00, 000000, 000001, 177736, 040000, 000000, 00
d=000000 --!
d=000000 --!
d=100000 --!00, 000000, 000001, 000037, 100000, 000000, 12 {left shift!}
d=000000 --!
d=000012 --!
#37330
d=100000 --!00, 000000, 000001, 177737, 000000, 000000, 04 {right shift!} !!->100000
d=000000 --!
d=000012 --! !!04->12
d=100000 --!00, 000000, 000001, 020037, 000000, 000000, 04 {right shift!} !!->100000
d=000000 --!
d=000012 --! !!04->12
# left shifts of negative numbers
d=177777 --!00, 177777, 177777, 000001, 177777, 177776, 11
d=177776 --!
d=000011 --!
d=177777 --!00, 177777, 177777, 000002, 177777, 177774, 11
d=177774 --!
d=000011 --!
#37360
d=140000 --!00, 177777, 177777, 000036, 140000, 000000, 11
d=000000 --!
d=000011 --!
d=100000 --!00, 177777, 177777, 000037, 100000, 000000, 11
d=000000 --!
d=000011 --!
d=000000 --!00, 177777, 177776, 000037, 000000, 000000, 07
d=000000 --!
d=000007 --!
d=000000 --!00, 177777, 177774, 000037, 000000, 000000, 06
d=000000 --!
d=000006 --!
#37410
d=177777 --!00, 177777, 177777, 177701, 177777, 177776, 11
d=177776 --!
d=000011 --!
d=100000 --!00, 177777, 177777, 001037, 177777, 177777, 11 {right shift!} !!->100000
d=000000 --! !!->00000
d=000011 --!
d=140000 --!00, 177777, 177777, 001036, 140000, 000000, 11
d=000000 --!
d=000011 --!
#-----------------------------------------------------------------------------
C Setup code 42 [base 12600] (systematic ASHC odd test)
#
wal 012600 -- code:
bwm 15
000230 -- spl 0
016401 -- L1: mov 2(r4),r1
000002
011412 -- mov (r4),(r2)
073164 -- ashc 4(r4),r1
000004
011265 -- mov (r2),2(r5)
000002
#12620
010115 -- mov r1,(r5)
062704 -- add #6,r4
000006
062705 -- add #4,r5
000004
077315 -- sob r3,L1
000000 -- halt
#
C Exec code 42 (systematic ASHC odd test)
C Exec test 42.1: data adapted from ashc.s11 code of Begemot p11-2.10c
#
# The {} comments are original comments from Harti Brandt
# Annotations starting with !! indicated mods for W11
# Note, that the W11 does not have the microcode bugs of the J11 !
#
wal 036000 -- setup test vector:
# test shift amount 0
bwm 165
000000 -- 00, 000000, 000000, 000000, 04
000000 --
000000 --
000017 -- 17, 000000, 000000, 000000, 04
000000 --
000000 --
000017 -- 17, 100001, 000000, 100001, 10
100001 --
000000 --
000017 -- 17, 040001, 000000, 040001, 00
040001 --
000000 --
000017 -- 17, 040001, 177700, 040001, 00
040001 --
177700 --
# right rotate positive values
000000 -- 00, 000000, 000077, 000000, 04
000000 --
000077 --
000017 -- 17, 000000, 000077, 000000, 04
000000 --
000077 --
000000 -- 00, 000002, 000077, 000001, 00
000002 --
000077 --
000000 -- 00, 000001, 000077, 100000, 01 {cc is funny!}
000001 --
000077 --
000000 -- 00, 000003, 000076, 140000, 01
000003 --
000076 --
000000 -- 00, 000001, 000076, 040000, 00
000001 --
000076 --
000000 -- 00, 040000, 000060, 040000, 00
040000 --
000060 --
000000 -- 00, 040000, 000043, 000002, 00
040000 --
000043 --
000000 -- 00, 040000, 000042, 000001, 00
040000 --
000042 --
000000 -- 00, 040000, 000041, 000000, 05
040000 --
000041 --
000000 -- 00, 040000, 000040, 000000, 04
040000 --
000040 --
000000 -- 00, 040000, 100037, 000000, 04
040000 --
100037 --
000000 -- 00, 020000, 000043, 000001, 00
020000 --
000043 --
000000 -- 00, 020000, 000042, 000000, 05
020000 --
000042 --
000000 -- 00, 020000, 000041, 000000, 04
020000 --
000041 --
# right rotate negative numbers
000000 -- 00, 100002, 000077, 040001, 10
100002 --
000077 --
000000 -- 00, 100002, 000076, 120000, 11
100002 --
000076 --
000000 -- 00, 100002, 000075, 050000, 10
100002 --
000075 --
000000 -- 00, 100002, 000061, 000005, 10
100002 --
000061 --
000000 -- 00, 100002, 000060, 100002, 11
100002 --
000060 --
000000 -- 00, 100002, 000057, 140001, 10
100002 --
000057 --
000000 -- 00, 100002, 000056, 160000, 11
100002 --
000056 --
000000 -- 00, 100002, 000055, 170000, 10
100002 --
000055 --
000000 -- 00, 100002, 000042, 177776, 10
100002 --
000042 --
000000 -- 00, 100002, 000041, 177777, 10
100002 --
000041 --
000000 -- 00, 100002, 000040, 177777, 11
100002 --
000040 --
000000 -- 00, 100002, 040037, 177777, 11
100002 --
040037 --
# left rotate positive numbers
000000 -- 00, 000000, 000001, 000000, 04
000000 --
000001 --
000000 -- 17, 000000, 000001, 000000, 04
000000 --
000001 --
000000 -- 00, 000001, 000007, 000200, 00
000001 --
000007 --
000000 -- 00, 000001, 000016, 040000, 00
000001 --
000016 --
000000 -- 00, 000001, 000017, 100000, 12
000001 --
000017 --
000000 -- 00, 000001, 000020, 000000, 03
000001 --
000020 --
000000 -- 00, 000001, 000021, 000000, 02
000001 --
000021 --
000000 -- 00, 000001, 000036, 000000, 02
000001 --
000036 --
000000 -- 00, 000001, 000037, 000000, 12
000001 --
000037 --
000000 -- 00, 000001, 000040, 000000, 04 {right shift!}
000001 --
000040 --
000000 -- 00, 000001, 010037, 000000, 04 {right shift!}
000001 --
010037 --
# left rotate negative numbers
000000 -- 00, 100001, 000001, 000002, 03
100001 --
000001 --
000000 -- 00, 140001, 000001, 100002, 11
140001 --
000001 --
000000 -- 00, 140001, 000002, 000004, 03
140001 --
000002 --
000000 -- 00, 140001, 000016, 040000, 02
140001 --
000016 --
000000 -- 00, 140001, 000017, 100000, 12
140001 --
000017 --
000000 -- 00, 140001, 000020, 000000, 13
140001 --
000020 --
000000 -- 00, 140001, 000021, 000000, 13
140001 --
000021 --
000000 -- 00, 140001, 000022, 000000, 03
140001 --
000022 --
000000 -- 00, 140001, 000023, 000000, 02
140001 --
000023 --
000000 -- 00, 140002, 000035, 000000, 02
140002 --
000035 --
000000 -- 00, 140002, 000036, 000000, 12
140002 --
000036 --
000000 -- 00, 140002, 000037, 000000, 07
140002 --
000037 --
#----
wr2 177776 -- r2=177776 -> psw
wr3 000067 -- r3=67 (55.) -> test count
wr4 036000 -- r4=36000 -> input area
wr5 037000 -- r5=37000 -> output area
wsp 001400 -- sp=1400
cres
stapc 012600 -- start @ 12600
wtgo
rpc d=012636 -- ! pc
rr3 d=000000 -- ! r3=0
rr4 d=036512 -- ! r4=36512
rr5 d=037334 -- ! r5=37334
wal 037000 --
# test shift amount 0
brm 110
d=000000 --!00, 000000, 000000, 000000, 04
d=000004 --!
d=000000 --!17, 000000, 000000, 000000, 04
d=000004 --!
d=100001 --!17, 100001, 000000, 100001, 10
d=000010 --!
d=040001 --!17, 040001, 000000, 040001, 00
d=000000 --!
#37020
d=040001 --!17, 040001, 177700, 040001, 00
d=000000 --!
# right rotate positive values
d=000000 --!00, 000000, 000077, 000000, 04
d=000004 --!
d=000000 --!17, 000000, 000077, 000000, 04
d=000004 --!
d=000001 --!00, 000002, 000077, 000001, 00
d=000000 --!
#37040
d=100000 --!00, 000001, 000077, 100000, 01 {cc is funny!}
d=000001 --!
d=140000 --!00, 000003, 000076, 140000, 01
d=000001 --!
d=040000 --!00, 000001, 000076, 040000, 00
d=000000 --!
d=040000 --!00, 040000, 000060, 040000, 00
d=000000 --!
#37060
d=000002 --!00, 040000, 000043, 000002, 00
d=000000 --!
d=000001 --!00, 040000, 000042, 000001, 00
d=000000 --!
d=000000 --!00, 040000, 000041, 000000, 05
d=000005 --!
d=000000 --!00, 040000, 000040, 000000, 04
d=000004 --!
#37100
d=000000 --!00, 040000, 100037, 000000, 04
d=000006 --! !!04->06
d=000001 --!00, 020000, 000043, 000001, 00
d=000000 --!
d=000000 --!00, 020000, 000042, 000000, 05
d=000005 --!
d=000000 --!00, 020000, 000041, 000000, 04
d=000004 --!
#37120 # right rotate negative numbers
d=040001 --!00, 100002, 000077, 040001, 10
d=000010 --!
d=120000 --!00, 100002, 000076, 120000, 11
d=000011 --!
d=050000 --!00, 100002, 000075, 050000, 10
d=000010 --!
d=000005 --!00, 100002, 000061, 000005, 10
d=000010 --!
#37140
d=100002 --!00, 100002, 000060, 100002, 11
d=000011 --!
d=140001 --!00, 100002, 000057, 140001, 10
d=000010 --!
d=160000 --!00, 100002, 000056, 160000, 11
d=000011 --!
d=170000 --!00, 100002, 000055, 170000, 10
d=000010 --!
#37160
d=177776 --!00, 100002, 000042, 177776, 10
d=000010 --!
d=177777 --!00, 100002, 000041, 177777, 10
d=000010 --!
d=177777 --!00, 100002, 000040, 177777, 11
d=000011 --!
d=000000 --!00, 100002, 040037, 177777, 11 !!->000000
d=000007 --! !!11->07
#37200 # left rotate positive numbers
d=000000 --!00, 000000, 000001, 000000, 04
d=000004 --!
d=000000 --!17, 000000, 000001, 000000, 04
d=000004 --!
d=000200 --!00, 000001, 000007, 000200, 00
d=000000 --!
d=040000 --!00, 000001, 000016, 040000, 00
d=000000 --!
#37220
d=100000 --!00, 000001, 000017, 100000, 12
d=000012 --!
d=000000 --!00, 000001, 000020, 000000, 03
d=000003 --!
d=000000 --!00, 000001, 000021, 000000, 02
d=000002 --!
d=000000 --!00, 000001, 000036, 000000, 02
d=000002 --!
#37240
d=000000 --!00, 000001, 000037, 000000, 12
d=000012 --!
d=000000 --!00, 000001, 000040, 000000, 04 {right shift!}
d=000004 --!
d=000000 --!00, 000001, 010037, 000000, 04 {right shift!}
d=000012 --! !!04->12
# left rotate negative numbers
d=000002 --!00, 100001, 000001, 000002, 03
d=000003 --!
#37260
d=100002 --!00, 140001, 000001, 100002, 11
d=000011 --!
d=000004 --!00, 140001, 000002, 000004, 03
d=000003 --!
d=040000 --!00, 140001, 000016, 040000, 02
d=000002 --!
d=100000 --!00, 140001, 000017, 100000, 12
d=000012 --!
#37300
d=000000 --!00, 140001, 000020, 000000, 13
d=000013 --!
d=000000 --!00, 140001, 000021, 000000, 13
d=000013 --!
d=000000 --!00, 140001, 000022, 000000, 03
d=000003 --!
d=000000 --!00, 140001, 000023, 000000, 02
d=000002 --!
#37320
d=000000 --!00, 140002, 000035, 000000, 02
d=000002 --!
d=000000 --!00, 140002, 000036, 000000, 12
d=000012 --!
d=000000 --!00, 140002, 000037, 000000, 07
d=000007 --!
#-----------------------------------------------------------------------------
C Setup code 43 [base 12700] (Begemot MARK instruction test)
# test data and code adapted from Mark.s11 code of Begemot p11-2.10c
#
wal 012700 -- code test 1: (basics)
bwm 14
012705 -- mov #77077,r5 ; cookie
077077
010546 -- mov r5,-(sp) ; push r5
012746 -- mov #12,-(sp) ; parameter 1
000012
012746 -- mov #23,-(sp) ; parameter 2
000023
012746 -- mov #mark+2,-(sp) ; now the mark instruction
#12720
006402
010605 -- mov sp,r5 ; let r5 point to mark instruction
004737 -- jsr pc,subr ; call subroutine
012770
000240 -- noop
000000 -- halt
#-----
wal 012740 -- code test 2: (MARK with max. # of args)
bwm 10
010546 -- mov r5, -(sp) ; push r5
162706 -- sub #2*77, sp ; max number
000176
012746 -- mov #mark+77, -(sp) ; the mark instruction
006477
010605 -- mov sp, r5 ; let r5 point to mark instruction
004737 -- jsr pc, subr ; call subroutine
012770
#12760
000240 -- noop
000000 -- halt
#-----
wal 012770 -- code (procedure):
wmi 000205 -- subr: rts r5
#-----
C Exec code 43 (Begemot MARK test)
C Exec test 43.1 (basics)
# D RE RQ FU DAT
wsp 001400 -- sp=1400
cres
stapc 012700 -- start @ 12700
wtgo
rpc d=012734 -- ! pc
rr5 d=077077 -- ! r5
rsp d=001400 -- ! sp
wal 001366 --
brm 5
d=012730 -- ! mem(1366)
d=006402 -- ! mem(1370)
d=000023 -- ! mem(1372)
d=000012 -- ! mem(1374)
d=077077 -- ! mem(1376)
#----
C Exec test 43.2 (MARK with max. # of args)
# D RE RQ FU DAT
wsp 001400 -- sp=1400
cres
stapc 012740 -- start @ 12740
wtgo
rpc d=012764 -- ! pc
rr5 d=077077 -- ! r5
rsp d=001400 -- ! sp
#-----------------------------------------------------------------------------
C Setup code 44 [base 13000] (Implementation variations)
# test various PDP11 implementation variations (DCJ11 user guide, table C-1)
#
wal 013000 -- code: (to be single stepped mostly)
bwm 22
010424 -- mov r4,(r4)+ ; case 1 and 2
010444 -- mov r4,-(r4)
010764 -- mov pc,2(r4)
000002
000124 -- jmp (r4)+
000104 -- jmp r4
000304 -- swab r4
005214 -- inc (r4)
#13020
000006 -- rtt
000000 -- halt
000002 -- rti
000000 -- halt
010011 -- mov r0,(r1)
010046 -- mov r0,-(sp)
000114 -- jmp (r4)
010021 -- mov r0,(r1)+
#13040
012100 -- mov (r1)+,r0
005221 -- inc (r1)+
106621 -- mtpd (r1)+
106506 -- mfpd sp
106606 -- mtpd sp
000003 -- bpt
#-----
wal 013070 -- code: (target for rtt,rti tests)
bwm 2
000240 -- noop
000000 -- halt
#-----
C Exec code 44 (Implementation variations)
C test 44.1: OPR R,(R)+ : incremented before {J11} or after {70} use as source
#
cres -- console reset
wps 000000 -- clear psw
wr4 001600 -- r4=1600
wsp 001400 -- sp=1400
wpc 013000 -- pc=13000
step -- step (mov r4,(r4)+)
rpc d=013002 -- ! pc=13002
rr4 d=001602 -- ! r4=1602
wal 001600 -- check target location
rmi d=001600 -- ! ; initial content of R expected for 11/70
#
C test 44.2: OPR R,-(R) : decremented before {J11} or after {70} use as source
#
wr4 001600 -- r4=1600
wsp 001400 -- sp=1400
wpc 013002 -- pc=13002
step -- step (mov r4,-(r4))
rpc d=013004 -- ! pc=13004
rr4 d=001576 -- ! r4=1576
wal 001600 -- check target location
rmi d=001600 -- ! ; initial content of R expected for 11/70
#
C test 44.3: OPR PC,A(R) : store PC+2 {70} or PC+4 {J11}
#
wr4 001600 -- r4=1600
wsp 001400 -- sp=1400
wpc 013004 -- pc=13004
step -- step (mov pc,2(r4))
rpc d=013010 -- ! pc=13010
wal 001602 -- check target location
rmi d=013006 -- ! ; PC+2 expected for 11/70
#
C test 44.4: JMP (R)+ : R used {70;J11} or R+2 used {05,10,15,20}
#
wr4 013074 -- r4=13074
wsp 001400 -- sp=1400
wpc 013010 -- pc=13010
step -- step (jmp (r4)+)
rpc d=013074 -- ! pc=13074 ; R expected for 11/70
rr4 d=013076 -- ! r4=13076
#
C test 44.5: JMP R : traps to 10 {44,45,70;J11} or 4 {all others}
C Note: J11 doc is wrong, 11/70 traps 10, not 4, as stated
#
wal 177766 -- clear CPUERR
wm 000000 --
wr4 000000 -- r4=0
wsp 001400 -- sp=1400
wpc 013012 -- pc=13012
step -- step (jmp r4) [[s:2]]
rpc d=000012 -- ! pc=12 ; trap 10 expected for 11/70 [[s:10]]
rsp d=001374 -- ! sp=1374
wal 177766 -- check CPUERR
rm d=000000 -- ! CPUERR: no bit set
wm 000000 -- clear CPUERR
#
C test 44.6: SWAB does not change V {15,20} or clears V {all others}
#
wr4 000300 -- r4=3000
wsp 001400 -- sp=1400
wpc 013014 -- pc=13014
wps 000017 -- psw: set all cc flags in psw
step -- step (swab r4)
rpc d=013016 -- ! pc=13074
rr4 d=140000 -- ! r4=140000
rps d=000004 -- ! psw: Z=1 ; clear V expected for 11/70
#
C test 44.7: CPU access to 177700-177717 (regs) timesout {70,J11} or not {05,10}
#
wr4 177700 -- r4=177700
wsp 001400 -- sp=1400
wpc 013016 -- pc=13016
step -- step (inc (r4)) [[s:2]]
rpc d=000006 -- ! pc=6 ; trap 4 expected for 11/70 [[s:10]]
rsp d=001374 -- ! sp=1374
wal 177766 -- check CPUERR
rm d=000020 -- ! CPUERR: (iobto=1)
wm 000000 -- clear CPUERR
#
C test 44.10: If RTT sets T bit, trap occurs after instr. following RTT {70,J11}
#
wal 001374 -- setup stack with rtt return frame setting T flag
bwm 2
013070 -- start address (points to: noop, halt)
000020 -- set T flag in PSW
wsp 001374 -- sp=1374
wpc 013020 -- pc=13020
sta -- start (rtt)
wtgo
rpc d=000020 -- ! pc=20 ; T-trap executed
rsp d=001374 -- ! sp=1374
wal 001374 -- check stack
brm 2
d=013072 -- trap address: address after noop expected for 11/70
d=000020 -- PSW
cres -- console reset (to clear T flag)
#
C test 44.11: If RTI sets T bit, T trap occurs immediately {70,J11}
#
wal 001374 -- setup stack with rtt return frame setting T flag
bwm 2
013070 -- start address (points to: noop, halt)
000020 -- set T flag in PSW
wsp 001374 -- sp=1374
wpc 013024 -- pc=13024
sta -- start (rti)
wtgo
rpc d=000020 -- ! pc=20 ; T-trap executed
rsp d=001374 -- ! sp=1374
wal 001374 -- check stack
brm 2
d=013070 -- trap address: address of noop expected for 11/70
d=000020 -- PSW
cres -- console reset (to clear T flag)
#
C test 44.14: Direct access to PSW can {05..20} / cannot {others} set T bit
#
wr0 000030 -- r0=30 (set T bit, N also)
wr1 177776 -- r1=177776 (PSW address)
wsp 001400 -- sp=1400
wpc 013030 -- pc=13030
step -- step (mov r0,(r1))
rpc d=013032 -- ! pc=13032
rps d=000010 -- ! psw: T bit not set expected for 11/70
#
C test 44.15: odd address using SP causes HALT {<=20} or emmergency stack {>35}
#
wsp 001401 -- sp=1401
wpc 013032 -- pc=13032
step -- step (mov r0,-(sp)) [[s:2]]
rpc d=000006 -- ! pc=6 ; trap 4 [[s:13034]]
rsp d=000000 -- ! sp=0 ; emergency stack expected for 11/70 [[s:4]]
wal 000000 -- check emergency stack
brm 2
d=013034 -- ! PC of abort [[s:0]]
d=000000 -- ! PS of abort (currently gets lost...)
cres -- console reset (to clear CPUERR reg)
wal 000000 -- clean tainted memory
bwm 2
000000 --
000000 --
#
# simh notes:
# 1. apparently not consistently implemented in simh. SP is set to 4, but
# interrupt/trap sequence isn't executed. Effectively, simh halt's.
#
# for the test 28/29/30x enable MMU and make address 100000 unavailable
#
wal 172310 -- kernel I space DR segment 4 (base 100000)
wmi 077400 -- slf=127; ed=0(up); acf=0 (non resident)
#
C test 44.28: If PC->bad memory, PC incremented {others} / not inc'ed {35,40}
#
cres
wal 177572 -- SSR0
wmi 000001 -- set enable bit
wr4 100000 -- r4=100000
wsp 001400 -- sp=1400
wpc 013034 -- pc=13034
sta -- start (jmp (r4))
wtgo
rpc d=000254 -- ! pc=254 ; trap 240 ; Note: halt is executed, was cont !
rsp d=001374 -- ! sp=1374
wal 001374 -- check stack
brm 2
d=100002 -- trap address: PC inc'ed expected for 11/70 [[s:100000]]
d=000340 -- PSW
cres -- console reset (to clear CPUERR reg)
#
# simh notes:
# 1. simh reads instruction, later increments PC. Thus PC not inc'ed in simh.
#
C test 44.29/30a: If R->bad in mode 2, R inc'ed {others} / or not {4,34,44}
C test for dstw chain (mov r0,(r1)+)
#
wal 177572 -- SSR0
wmi 000001 -- set enable bit
wr1 100000 -- r1=100000
wsp 001400 -- sp=1400
wpc 013036 -- pc=13036
step -- step (mov r0,(r1)+) [[s:2]]
rpc d=000252 -- ! pc=252 ; trap 250 [[s:254]]
rsp d=001374 -- ! sp=1374
rr1 d=100002 -- ! r1=100002
wal 177572 -- check SSR0/1
brm 2
d=100011 -- ! SSR0: (abo_nonres=1,seg=4,ena=1) see note [[s:100211]]
d=000021 -- ! SSR1: ra=1,2
cres -- console reset (to clear CPUERR reg)
#
C test 44.29/30b: If R->bad in mode 2, R inc'ed {others} / or not {4,34,44}
C test for srcr chain (mov (r1)+,r0)
#
wal 177572 -- SSR0
wmi 000001 -- set enable bit
wr1 100000 -- r1=100000
wsp 001400 -- sp=1400
wpc 013040 -- pc=13040
step -- step ((mov (r1)+,r0) [[s:2]]
rpc d=000252 -- ! pc=252 ; trap 250 [[s:254]]
rsp d=001374 -- ! sp=1374
rr1 d=100002 -- ! r1=100002
wal 177572 -- check SSR0/1
brm 2
d=100011 -- ! SSR0: (abo_nonres=1,seg=4,ena=1) see note [[s:100211]]
d=000021 -- ! SSR1: ra=1,2
cres -- console reset (to clear CPUERR reg)
#
C test 44.29/30c: If R->bad in mode 2, R inc'ed {others} / or not {4,34,44}
C test for dstr chain (inc (r1)+)
#
wal 177572 -- SSR0
wmi 000001 -- set enable bit
wr1 100000 -- r1=100000
wsp 001400 -- sp=1400
wpc 013042 -- pc=13042
step -- step (inc (r1)+) [[s:2]]
rpc d=000252 -- ! pc=252 ; trap 250 [[s:254]]
rsp d=001374 -- ! sp=1374
rr1 d=100002 -- ! r1=100002
wal 177572 -- check SSR0/1
brm 2
d=100011 -- ! SSR0: (abo_nonres=1,seg=4,ena=1) see note [[s:100211]]
d=000021 -- ! SSR1: ra=1,2
cres -- console reset (to clear CPUERR reg)
C test 44.29/30d: If R->bad in mode 2, R inc'ed {others} / or not {4,34,44}
C test for dsta chain (mtpd (r1)+)
#
wal 177572 -- SSR0
wmi 000001 -- set enable bit
wr1 100000 -- r1=100000
wsp 001376 -- sp=1376
wpc 013044 -- pc=13044
wal 001376 -- push a word on stack for mtpd
wmi 123456 --
step -- step (mtpd (r1)+) [[s:2]]
rpc d=000252 -- ! pc=252 ; trap 250 [[s:254]]
rsp d=001374 -- ! sp=1374
rr1 d=100002 -- ! r1=100002
wal 177572 -- check SSR0/1
brm 2
d=100011 -- ! SSR0: (abo_nonres=1,seg=4,ena=1) see note [[s:100211]]
d=010426 -- ! SSR1: rb=1,2; ra=6,2
cres -- console reset (to clear CPUERR reg)
#
# simh notes:
# 1. simh first pops, than writes to destination, reversing ra,rb in SSR1
#
# now reset MMU to default
#
wal 172310 -- kernel I space DR segment 4 (base 100000)
wmi 077406 -- slf=127; ed=0(up); acf=6 (r/w)
#
C test 44.39: cmode=10 will cause abort {70,J11}, treated as kmode {23,24}
#
wal 177572 -- SSR0
wmi 000001 -- set enable bit
wr1 001400 -- r1=1400
wsp 001400 -- sp=1400
wps 100000 -- psw: set cm=10, pm=00
wpc 013042 -- pc=13042
step -- step (inc (r1)+) [[s:2]]
rpc d=000252 -- ! pc=252 ; trap 250; as expected for 11/70 [[s:254]]
rsp d=001374 -- ! sp=1374
rr1 d=001400 -- ! r1=1400
wal 177572 -- check SSR0/1
brm 3
d=140101 -- ! SSR0: (abo_nr=1,abo_l=1,m=10,seg=0,ena=1) [[s:140301]]
d=000000 -- ! SSR1: ra=none
d=013042 -- ! SSR2: PC of failed instruction
wal 001374 -- check stack
brm 2
d=013044 -- ! PC after failed instruction [[s:013042]]
d=100000 -- ! PS
cres -- console reset (to clear CPUERR reg, PSW)
#
# simh notes:
# 1. simh saves PC of failed instruction on stack, not PC after instruction
#
C test 44.43: user mode HALT: trap 4 {70} or 10 {others}
#
wal 177766 -- check CPUERR ;??? remove if console reset fixed
wm 000000 -- clear
wsp 001400 -- sp=1400
wps 170000 -- psw: set cm=11, pm=11
wpc 013022 -- pc=13022
step -- step (halt in user mode) [[s:2]]
rpc d=000006 -- ! pc=6 ; trap 4; as expected for 11/70 [[s:10]]
rsp d=001374 -- ! sp=1374
wal 001374 -- check stack
brm 2
d=013024 -- ! PC after failed instruction
d=170000 -- ! PS
wal 177766 -- check CPUERR
rm d=000200 -- ! CPUERR: (illhalt=1)
cres -- console reset (to clear CPUERR reg, PSW)
#
C test 44.44: PDR bit<0> implemented {70} or not {others}
#
wal 172310 -- kernel I space DR, segment 4
wm 077401 -- set acf bit 0: slf=127; ed=0(up); acf=1 (r+trap)
rm d=077401 -- ! check; works as expected for 11/70
wm 077406 -- restore: slf=127; ed=0(up); acf=6(w/r)
#
C test 44.45: PDR bit<7>(AIB any access) implemented {70} or not {others}
#
wal 172300 -- kernel I space DR, reset segment 0 and 1
bwm 2
077404 -- slf=127; ed=0(up); acf=4(w/r and trap)
077404 -- slf=127; ed=0(up); acf=4(w/r and trap)
wal 172300 -- check kernel I space DR, segment 0 and 1
brm 2
d=077404 -- !
d=077404 -- !
wal 177572 -- SSR0
wmi 000001 -- set enable bit
wr0 123456 -- r0=123456
wr1 030000 -- r1=30000
wsp 001400 -- sp=1400
wpc 013030 -- pc=13030
step -- step (mov r0,(r1))
rpc d=013032 -- ! pc=next
rsp d=001400 -- ! sp=1400
wal 030000 -- check target memory, untaint
rm d=123456 -- !
wm 000000 --
wal 172300 -- check kernel I space DR, segment 0 and 1
brm 2
d=077604 -- ! slf=127; ed=0(up); acf=4(w/r+trap); aib=10 (A=1,W=0)
d=077704 -- ! slf=127; ed=0(up); acf=4(w/r+trap); aib=11 (A=1,W=1)
wal 172300 -- kernel I space DR, reset segment 0 and 1
bwm 2
077406 -- slf=127; ed=0(up); acf=6(w/r)
077406 -- slf=127; ed=0(up); acf=6(w/r)
cres -- console reset (to clear CPUERR reg)
#
C test 44.46: Full PAR implemented {44,70,J11} or not {others}
#
wal 172350 -- kernel I space AR, segment 4
wm 177777 -- set all bits
rm d=177777 -- ! check; works as expected for 11/70
wm 001000 -- restore: 1000 100000 base
#
C test 44.47: MMR0<9>(mmu trap) implemented {70} or not {others}
#
wal 177572 -- SSR0
wm 001000 -- set trap enable
rm d=001000 -- ! check; works as expected for 11/70
wm 000000 -- restore
#
C test 44.48: MMR3<2:0>(D space) implemented {44,70,J11} or not {others}
#
wal 172516 -- SSR3
wm 000007 -- set D space bis
rm d=000007 -- ! check; works as expected for 11/70
wm 000000 -- restore
#
C test 44.49: MMR3<5:4>(UMAP, 22 bit) implemented {44,70,J11} or not {others}
#
wal 172516 -- SSR3
wm 000060 -- set D space bits
rm d=000060 -- ! check; available, as expected for 11/70
wm 000000 -- restore
#
C test 44.50: MMR3<3>(CSM enable) implemented {44,J11} or not {others}
#
wal 172516 -- SSR3
wm 000010 -- set D space bit
rm d=000000 -- ! check; not available, as expected for 11/70
wm 000000 -- restore
#
C test 44.51: MMR2 tracks fetches {70} or instructions only {others}
C here W11 behaves like {others}, fetches are not tracked in SSR2
C Also: instruction complete flag set in SSR0 after bpt.
#
wal 177572 -- SSR0
wmi 000001 -- set enable bit
wsp 001400 -- sp=1400
wpc 013052 -- pc=13052
step -- step (bpt)
rpc d=000016 -- ! pc=16; trap 14 see note [[s:13054]]
wal 177572 -- check SSR0/1/2
brm 3
d=000001 -- ! SSR0: (ena=1)
d=000000 -- ! SSR1: ra=none
d=013052 -- ! SSR2: PC of bpt
step -- step (halt)
rpc d=000020 -- ! pc=20 (after halt)
wal 177572 -- check SSR0/1/2
brm 3
d=000001 -- ! SSR0: (ena=1)
d=000000 -- ! SSR1: ra=none
d=000016 -- ! SSR2: PC of halt
cres -- console reset (to clear CPUERR reg, PSW)
#
# simh notes:
# 1. when simh steps over a BPT,IOT,..., the PC is pointing after the
# instruction. The trap sequence together with first instruction is
# executed in next step.
#
C test 44.52: MT/FPx SP for pmode=10 unpredictable {others} / user SP {J11}
# write registers
#
wr0 000001 -- set r0,..,r7
wr1 000101 --
wr2 000201 --
wr3 000301 --
wr4 000401 --
wr5 000501 --
wsp 001400 --
wpc 000701 --
# write register set 1, sm,um stack
#
wps 004000 -- psw: cm=kernel, set=1
wr0 010001 -- set r0,..,r5 [[r10]]
wr1 010101 -- [[r11]]
wr2 010201 -- [[r12]]
wr3 010301 -- [[r13]]
wr4 010401 -- [[r14]]
wr5 010501 -- [[r15]]
wps 044000 -- psw: cm=super(01),set=1
wsp 010601 -- set ssp [[ssp]]
wps 144000 -- psw: cm=user(11),set=1
wsp 110601 -- set usp [[usp]]
#
C 52a: MFPS for pmode=10
#
wps 020000 -- psw: set cm=00, pm=10
wpc 013046 -- pc=13046
step -- step (mfpd sp)
rpc d=013050 -- ! pc=next
rsp d=001376 -- ! sp=1376
wal 001376 -- check stack
rmi d=013046 -- ! it returns PC like 11/70 unpredictable [[s:0]]
cres -- console reset (to clear CPUERR reg)
#
# simh note:
# 1. simh returns 0 here, just unpredictable in a different way ...
#
C 52a: MTPS for pmode=10
#
wal 001376 -- setup stack with value for mtpd
wmi 123446 --
wps 020000 -- psw: set cm=00, pm=10
wpc 013050 -- pc=13050
step -- step (mtpd sp)
rpc d=013052 -- ! pc=next
rsp d=001400 -- ! sp=1400
# check registers
#
rr0 d=000001 -- ! r0,..,r7
rr1 d=000101 -- !
rr2 d=000201 -- !
rr3 d=000301 -- !
rr4 d=000401 -- !
rr5 d=000501 -- !
# check register set 1, sm,um stack
#
wps 004000 -- psw: cm=kernel, set=1
rr0 d=010001 -- ! r0,..,r5 [[r10]]
rr1 d=010101 -- ! [[r11]]
rr2 d=010201 -- ! [[r12]]
rr3 d=010301 -- ! [[r13]]
rr4 d=010401 -- ! [[r14]]
rr5 d=010501 -- ! [[r15]]
wps 044000 -- psw: cm=super(01),set=1
rsp d=010601 -- ! ssp [[ssp]]
wps 144000 -- psw: cm=user(11),set=1
rsp d=110601 -- ! usp [[usp]]
# --> all preset values intact; -> mtpd thus noop --> like 11/70 unpredictable
#
cres -- console reset (to clear CPUERR reg)
#
# simh notes on MMR0:
# 1. simh doesn't freeze MMR0 bit 7, the instr.compl. bit is set again after
# executing first instruction of trap handler.
#
#-----------------------------------------------------------------------------
C Setup code 45 [base 13100] (mmr1 and instructions with implicit stack push/pop
#
wal 013100 -- code: (to be single stepped mostly)
bwm 5
106621 -- mtpd (r1)+
106521 -- mfpd (r1)+
004721 -- jsr pc,(r1)+
000000 -- halt
#13110
000207 -- rts pc
#-----
C Exec code 45 (mmr1 and instructions with implicit stack push/pop)
C test 45.1: mtpd (r1)+
#
cres
wal 177572 -- SSR0
wmi 000001 -- set enable bit
wal 001376 -- setup stack with value for mtpd
wmi 123456 --
wr1 030000 -- r1=30000
wsp 001376 -- sp=1376
wpc 013100 -- pc=13100
step -- step (mtpd (r1)+)
rpc d=013102 -- ! pc=next
rsp d=001400 -- ! sp=1400
rr1 d=030002 -- ! r1=30002
wal 177572 -- check SSR0/1/2
brm 3
d=000003 -- ! SSR0: (seg=1,ena=1)
d=010426 -- ! SSR1: rb=1,2; ra=6,2
d=013100 -- ! SSR2: PC of mtpd
wal 030000 -- check target memory
rm d=123456 -- !
cres -- console reset
#
C test 45.2: mfpd (r1)+
#
wal 177572 -- SSR0
wmi 000001 -- set enable bit
wr1 030000 -- r1=30000
wsp 001400 -- sp=1400
wpc 013102 -- pc=13102
step -- step (mfpd (r1)+)
rpc d=013104 -- ! pc=next
rsp d=001376 -- ! sp=1376
rr1 d=030002 -- ! r1=30002
wal 177572 -- check SSR0/1/2
brm 3
d=000001 -- ! SSR0: (seg=0,ena=1)
d=173021 -- ! SSR1: rb=6,-2; ra=1,2
d=013102 -- ! SSR2: PC of mtpd
wal 001376 -- check stack
rmi d=123456 -- !
wal 030000 -- clear tainted target memory
wm 000000 --
cres -- console reset
#
C test 45.3: jsr pc,(r1)+ and rts pc
#
wal 177572 -- SSR0
wmi 000001 -- set enable bit
wr1 013110 -- r1=13110
wsp 001400 -- sp=1400
wpc 013104 -- pc=13104
step -- step (jsr pc,(r1)+)
rpc d=013110 -- ! pc=target
rsp d=001376 -- ! sp=1376
rr1 d=013112 -- ! r1=13112
wal 177572 -- check SSR0/1/2
brm 3
d=000001 -- ! SSR0: (seg=0,ena=1)
d=173021 -- ! SSR1: rb=6,-2; ra=1,2
d=013104 -- ! SSR2: PC of jsr
wal 001376 -- check stack
rmi d=013106 -- ! PC after jsr
step -- step (rts pc)
rpc d=013106 -- ! pc=target
rsp d=001400 -- ! sp=1400
wal 177572 -- check SSR0/1/2
brm 3
d=000001 -- ! SSR0: (seg=0,ena=1)
d=000026 -- ! SSR1: ra=6,2 [[s:0]]
d=013110 -- ! SSR2: PC of rts
cres -- console reset
#
# simh notes:
# 1. simh reads stack and incremets sp later. In case of an MMU abort on
# stack read, simh SSR1 will be 0, while W11 shows the sp increment
#
#-----------------------------------------------------------------------------
C Setup code 46 [base 13200] (systematic result+cc test of 1+2op instructions)
# the following codes expect:
# r0-> psw
# r1-> loop count
# r2-> input ptr
# r3-> output ptr
# r4-> src reg
# r5-> dst reg
#
wal 013200 -- code 1: test 1op register
bwm 8
000230 -- spl 0
012205 -- L1: mov (r2)+,r5 ; load dst
000000 -- halt ; ccmov set cc's
000000 -- halt ; iut instr. under test
011023 -- mov (r0),(r3)+ ; save psw
010523 -- mov r5,(r3)+ ; save dst
077106 -- sob r1,L1 (.-6)
000000 -- halt
#----
wal 013220 -- code 2: test 1op memory
bwm 8
000230 -- spl 0
012215 -- L1: mov (r2)+,(r5) ; load dst
000000 -- halt ; ccmov set cc's
000000 -- halt ; iut instr. under test
011023 -- mov (r0),(r3)+ ; save psw
011523 -- mov (r5),(r3)+ ; save dst
077106 -- sob r1,L1 (.-6)
000000 -- halt
#-----
wal 013240 -- code 3: test 2op register
bwm 9
000230 -- spl 0
012204 -- L1: mov (r2)+,r4 ; load src
012205 -- mov (r2)+,r5 ; load dst
000000 -- halt ; ccmov set cc's
000000 -- halt ; iut instr. under test
011023 -- mov (r0),(r3)+ ; save psw
010523 -- mov r5,(r3)+ ; save dst
077107 -- sob r1,L1 (.-7)
#13260
000000 -- halt
#-----
wal 013270 -- code 4: test 2op memory
bwm 9
000230 -- spl 0
012214 -- L1: mov (r2)+,(r4) ; load src
012215 -- mov (r2)+,(r5) ; load dst
000000 -- halt ; ccmov set cc's
#13300
000000 -- halt ; iut instr. under test
011023 -- mov (r0),(r3)+ ; save psw
011523 -- mov (r5),(r3)+ ; save dst
077107 -- sob r1,L1 (.-7)
000000 -- halt
#----
C Exec code 46 pass 1 (systematic result+cc test of 1+2op instructions; word)
C Exec test 46.1wr: COM - reg
#
wal 036000 -- setup test vector: for com,inc,dec,neg,adc,sbc,tst
bwm 5
000000 -- com 000000
000001 -- com 000001
077777 -- com 077777
100000 -- com 100000
177777 -- com 177777
wal 013204 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
005105 -- iut= com r5
wr0 177776 -- r0=177776
wr1 000005 -- r1=5
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
cres
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 10
d=000011 -- ! com 000000 -> n1z0v0c1; 177777
d=177777 -- !
d=000011 -- ! com 000001 -> n1z0v0c1; 177776
d=177776 -- !
d=000011 -- ! com 077777 -> n1z0v0c1; 100000
d=100000 -- !
d=000001 -- ! com 100000 -> n0z0v0c1; 077777
d=077777 -- !
d=000005 -- ! com 177777 -> n0z1v0c1; 000000
d=000000 -- !
#--------
C Exec test 46.1wm: COM - mem
#
wal 013224 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
005115 -- iut= com (r5)
wr0 177776 -- r0=177776
wr1 000005 -- r1=5
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 001400 -- r4=1400
wr5 001402 -- r5=1402
wsp 001400 -- sp=1400
cres
stapc 013220 -- start @ 13220 (1op mem)
wtgo
rpc d=013240 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 10
d=000011 -- ! com 000000 -> n1z0v0c1; 177777
d=177777 -- !
d=000011 -- ! com 000001 -> n1z0v0c1; 177776
d=177776 -- !
d=000011 -- ! com 077777 -> n1z0v0c1; 100000
d=100000 -- !
d=000001 -- ! com 100000 -> n0z0v0c1; 077777
d=077777 -- !
d=000005 -- ! com 177777 -> n0z1v0c1; 000000
d=000000 -- !
#--------
C Exec test 46.2wrc0: INC - reg,C=0
#
wal 013204 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
005205 -- iut= inc r5
wr0 177776 -- r0=177776
wr1 000005 -- r1=5
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
cres
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 10
d=000000 -- ! inc 000000 -> n0z0v0c0; 000001
d=000001 -- !
d=000000 -- ! inc 000001 -> n0z0v0c0; 000002
d=000002 -- !
d=000012 -- ! inc 077777 -> n1z0v1c0; 100000
d=100000 -- !
d=000010 -- ! inc 100000 -> n1z0v0c0; 100001
d=100001 -- !
d=000004 -- ! inc 177777 -> n0z1v0c0; 000000
d=000000 -- !
#--------
C Exec test 46.2wrc1: INC - reg,C=1
#
wal 013204 -- setup test instructions:
bwm 2
000261 -- ccmov= sec
005205 -- iut= inc r5
wr0 177776 -- r0=177776
wr1 000005 -- r1=5
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
cres
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 10
d=000001 -- ! inc 000000 -> n0z0v0c1; 000001
d=000001 -- !
d=000001 -- ! inc 000001 -> n0z0v0c1; 000002
d=000002 -- !
d=000013 -- ! inc 077777 -> n1z0v1c1; 100000
d=100000 -- !
d=000011 -- ! inc 100000 -> n1z0v0c1; 100001
d=100001 -- !
d=000005 -- ! inc 177777 -> n0z1v0c1; 000000
d=000000 -- !
#--------
C Exec test 46.3wrc0: DEC - reg,C=0
#
wal 013204 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
005305 -- iut= dec r5
wr0 177776 -- r0=177776
wr1 000005 -- r1=5
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
cres
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 10
d=000010 -- ! dec 000000 -> n1z0v0c0; 177777
d=177777 -- !
d=000004 -- ! dec 000001 -> n0z1v0c0; 000000
d=000000 -- !
d=000000 -- ! dec 077777 -> n0z0v0c0; 077776
d=077776 -- !
d=000002 -- ! dec 100000 -> n0z0v1c0; 077777
d=077777 -- !
d=000010 -- ! dec 177777 -> n1z0v0c0; 177776
d=177776 -- !
#--------
C Exec test 46.3wrc1: DEC - reg,C=1
#
wal 013204 -- setup test instructions:
bwm 2
000261 -- ccmov= sec
005305 -- iut= dec r5
wr0 177776 -- r0=177776
wr1 000005 -- r1=5
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
cres
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 10
d=000011 -- ! dec 000000 -> n1z0v0c1; 177777
d=177777 -- !
d=000005 -- ! dec 000001 -> n0z1v0c1; 000000
d=000000 -- !
d=000001 -- ! dec 077777 -> n0z0v0c1; 077776
d=077776 -- !
d=000003 -- ! dec 100000 -> n0z0v1c1; 077777
d=077777 -- !
d=000011 -- ! dec 177777 -> n1z0v0c1; 177776
d=177776 -- !
#--------
C Exec test 46.4wr: NEG - reg
#
wal 013204 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
005405 -- iut= neg r5
wr0 177776 -- r0=177776
wr1 000005 -- r1=5
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
cres
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 10
d=000004 -- ! neg 000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000011 -- ! neg 000001 -> n1z0v0c1; 177777
d=177777 -- !
d=000011 -- ! neg 077777 -> n1z0v0c1; 100001
d=100001 -- !
d=000013 -- ! neg 100000 -> n1z0v1c1; 100000
d=100000 -- !
d=000001 -- ! neg 177777 -> n0z0v0c1; 000001
d=000001 -- !
#--------
C Exec test 46.5wrc0: ADC - reg,C=0
#
wal 013204 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
005505 -- iut= adc r5
wr0 177776 -- r0=177776
wr1 000005 -- r1=5
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
cres
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 10
d=000004 -- ! adc 000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000000 -- ! adc 000001 -> n0z0v0c0; 000001
d=000001 -- !
d=000000 -- ! adc 077777 -> n0z0v0c0; 077777
d=077777 -- !
d=000010 -- ! adc 100000 -> n1z0v0c0; 100000
d=100000 -- !
d=000010 -- ! adc 177777 -> n1z0v0c0; 177777
d=177777 -- !
#--------
C Exec test 46.5wrc1: ADC - reg,C=1
#
wal 013204 -- setup test instructions:
bwm 2
000261 -- ccmov= sec
005505 -- iut= adc r5
wr0 177776 -- r0=177776
wr1 000005 -- r1=5
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
cres
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 10
d=000000 -- ! adc 000000 -> n0z0v0c0; 000001
d=000001 -- !
d=000000 -- ! adc 000001 -> n0z0v0c0; 000002
d=000002 -- !
d=000012 -- ! adc 077777 -> n1z0v1c0; 100000
d=100000 -- !
d=000010 -- ! adc 100000 -> n1z0v0c0; 100001
d=100001 -- !
d=000005 -- ! adc 177777 -> n0z1v0c1; 000000
d=000000 -- !
#--------
C Exec test 46.6wrc0: SBC - reg,C=0
#
wal 013204 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
005605 -- iut= sbc r5
wr0 177776 -- r0=177776
wr1 000005 -- r1=5
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
cres
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 10
d=000004 -- ! sbc 000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000000 -- ! sbc 000001 -> n0z0v0c0; 000001
d=000001 -- !
d=000000 -- ! sbc 077777 -> n0z0v0c0; 077777
d=077777 -- !
d=000010 -- ! sbc 100000 -> n1z0v0c0; 100000
d=100000 -- !
d=000010 -- ! sbc 177777 -> n1z0v0c0; 177777
d=177777 -- !
#--------
C Exec test 46.6wrc1: SBC - reg,C=1
#
wal 013204 -- setup test instructions:
bwm 2
000261 -- ccmov= sec
005605 -- iut= sbc r5
wr0 177776 -- r0=177776
wr1 000005 -- r1=5
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
cres
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 10
d=000011 -- ! sbc 000000 -> n1z0v0c1; 177777
d=177777 -- !
d=000004 -- ! sbc 000001 -> n0z1v0c0; 000000
d=000000 -- !
d=000000 -- ! sbc 077777 -> n0z0v0c0; 077776
d=077776 -- !
d=000002 -- ! sbc 100000 -> n0z0v1c0; 077777
d=077777 -- !
d=000010 -- ! sbc 177777 -> n1z0v0c0; 177776
d=177776 -- !
#--------
C Exec test 46.7wr: TST - reg
#
wal 013204 -- setup test instructions:
bwm 2
000261 -- ccmov= sec
005705 -- iut= tst r5
wr0 177776 -- r0=177776
wr1 000005 -- r1=5
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
cres
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 10
d=000004 -- ! tst 000000 -> n0z1v0c0;
d=000000 -- !
d=000000 -- ! tst 000001 -> n0z0v0c0;
d=000001 -- !
d=000000 -- ! tst 077777 -> n0z0v0c0;
d=077777 -- !
d=000010 -- ! tst 100000 -> n1z0v0c0;
d=100000 -- !
d=000010 -- ! tst 177777 -> n1z0v0c0;
d=177777 -- !
#--------
C Exec test 46.7wm: TST - mem
#
wal 013224 -- setup test instructions:
bwm 2
000261 -- ccmov= sec
005715 -- iut= tst (r5)
wr0 177776 -- r0=177776
wr1 000005 -- r1=5
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 001400 -- r4=1400
wr5 001402 -- r5=1402
wsp 001400 -- sp=1400
cres
stapc 013220 -- start @ 13220 (1op mem)
wtgo
rpc d=013240 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 10
d=000004 -- ! tst 000000 -> n0z1v0c0;
d=000000 -- !
d=000000 -- ! tst 000001 -> n0z0v0c0;
d=000001 -- !
d=000000 -- ! tst 077777 -> n0z0v0c0;
d=077777 -- !
d=000010 -- ! tst 100000 -> n1z0v0c0;
d=100000 -- !
d=000010 -- ! tst 177777 -> n1z0v0c0;
d=177777 -- !
#--------
C Exec test 46.8wrc0: ROR - reg, C=0
#
wal 036000 -- setup test vector: for ror,rol,ars,asl
bwm 7
000000 -- ror 000000
000001 -- ror 000001
100000 -- ror 100000
000100 -- ror 000100
000101 -- ror 000101
040100 -- ror 040100
100100 -- ror 100100
wal 013204 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
006005 -- iut= ror r5
wr0 177776 -- r0=177776
wr1 000007 -- r1=7
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
cres
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area (Note: V = N xor C !)
brm 14
d=000004 -- ! ror 000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000007 -- ! ror 000001 -> n0z1v1c1; 000000
d=000000 -- !
d=000000 -- ! ror 100000 -> n0z0v0c0; 040000
d=040000 -- !
d=000000 -- ! ror 000100 -> n0z0v0c0; 000040
d=000040 -- !
d=000003 -- ! ror 000101 -> n0z0v1c1; 000040
d=000040 -- !
d=000000 -- ! ror 040100 -> n0z0v0c0; 020040
d=020040 -- !
d=000000 -- ! ror 100100 -> n0z0v0c0; 040040
d=040040 -- !
#--------
C Exec test 46.8wrc1: ROR - reg, C=1
#
wal 013204 -- setup test instructions:
bwm 2
000261 -- ccmov= sec
006005 -- iut= ror r5
wr0 177776 -- r0=177776
wr1 000007 -- r1=7
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
cres
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area (Note: V = N xor C !)
brm 14
d=000012 -- ! ror 000000 -> n1z0v1c0; 100000
d=100000 -- !
d=000011 -- ! ror 000001 -> n1z0v0c1; 100000
d=100000 -- !
d=000012 -- ! ror 100000 -> n1z0v1c0; 140000
d=140000 -- !
d=000012 -- ! ror 000100 -> n1z0v1c0; 100040
d=100040 -- !
d=000011 -- ! ror 000101 -> n1z0v0c1; 100040
d=100040 -- !
d=000012 -- ! ror 040100 -> n1z0v1c0; 120040
d=120040 -- !
d=000012 -- ! ror 100100 -> n1z0v1c0; 140040
d=140040 -- !
#--------
C Exec test 46.9wrc0: ROL - reg, C=0
#
wal 013204 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
006105 -- iut= rol r5
wr0 177776 -- r0=177776
wr1 000007 -- r1=7
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
cres
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area (Note: V = N xor C !)
brm 14
d=000004 -- ! rol 000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000000 -- ! rol 000001 -> n0z0v0c0; 000002
d=000002 -- !
d=000007 -- ! rol 100000 -> n0z1v1c1; 000000
d=000000 -- !
d=000000 -- ! rol 000100 -> n0z0v0c0; 000200
d=000200 -- !
d=000000 -- ! rol 000101 -> n0z0v0c0; 000202
d=000202 -- !
d=000012 -- ! rol 040100 -> n1z0v1c0; 100200
d=100200 -- !
d=000003 -- ! rol 100100 -> n0z0v1c1; 000200
d=000200 -- !
#--------
C Exec test 46.9wrc1: ROL - reg, C=1
#
wal 013204 -- setup test instructions:
bwm 2
000261 -- ccmov= sec
006105 -- iut= rol r5
wr0 177776 -- r0=177776
wr1 000007 -- r1=7
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
cres
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area (Note: V = N xor C !)
brm 14
d=000000 -- ! rol 000000 -> n0z0v0c0; 000001
d=000001 -- !
d=000000 -- ! rol 000001 -> n0z0v0c0; 000003
d=000003 -- !
d=000003 -- ! rol 100000 -> n0z0v1c1; 000001
d=000001 -- !
d=000000 -- ! rol 000100 -> n0z0v0c0; 000201
d=000201 -- !
d=000000 -- ! rol 000101 -> n0z0v0c0; 000203
d=000203 -- !
d=000012 -- ! rol 040100 -> n1z0v1c0; 100201
d=100201 -- !
d=000003 -- ! rol 100100 -> n0z0v1c1; 000201
d=000201 -- !
#--------
C Exec test 46.10wrc0: ASR - reg, C=0
#
wal 013204 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
006205 -- iut= asr r5
wr0 177776 -- r0=177776
wr1 000007 -- r1=7
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
cres
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area (Note: V = N xor C !)
brm 14
d=000004 -- ! asr 000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000007 -- ! asr 000001 -> n0z1v1c1; 000000
d=000000 -- !
d=000012 -- ! asr 100000 -> n1z0v1c0; 140000
d=140000 -- !
d=000000 -- ! asr 000100 -> n0z0v0c0; 000040
d=000040 -- !
d=000003 -- ! asr 000101 -> n0z0v1c1; 000040
d=000040 -- !
d=000000 -- ! asr 040100 -> n0z0v0c0; 020040
d=020040 -- !
d=000012 -- ! asr 100100 -> n1z0v1c0; 140040
d=140040 -- !
#--------
C Exec test 46.10wrc1: ASR - reg, C=1
#
wal 013204 -- setup test instructions:
bwm 2
000261 -- ccmov= sec
006205 -- iut= asr r5
wr0 177776 -- r0=177776
wr1 000007 -- r1=7
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
cres
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area (Note: V = N xor C !)
brm 14
d=000004 -- ! asr 000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000007 -- ! asr 000001 -> n0z1v1c1; 000000
d=000000 -- !
d=000012 -- ! asr 100000 -> n1z0v1c0; 140000
d=140000 -- !
d=000000 -- ! asr 000100 -> n0z0v0c0; 000040
d=000040 -- !
d=000003 -- ! asr 000101 -> n0z0v1c1; 000040
d=000040 -- !
d=000000 -- ! asr 040100 -> n0z0v0c0; 020040
d=020040 -- !
d=000012 -- ! asr 100100 -> n1z0v1c0; 140040
d=140040 -- !
#--------
C Exec test 46.11wrc0: ASL - reg, C=0
#
wal 013204 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
006305 -- iut= asl r5
wr0 177776 -- r0=177776
wr1 000007 -- r1=7
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
cres
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area (Note: V = N xor C !)
brm 14
d=000004 -- ! asl 000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000000 -- ! asl 000001 -> n0z0v0c0; 000002
d=000002 -- !
d=000007 -- ! asl 100000 -> n0z1v1c1; 000000
d=000000 -- !
d=000000 -- ! asl 000100 -> n0z0v0c0; 000200
d=000200 -- !
d=000000 -- ! asl 000101 -> n0z0v0c0; 000202
d=000202 -- !
d=000012 -- ! asl 040100 -> n1z0v1c0; 100200
d=100200 -- !
d=000003 -- ! asl 100100 -> n0z0v1c1; 000200
d=000200 -- !
#--------
C Exec test 46.11wrc1: ASL - reg, C=1
#
wal 013204 -- setup test instructions:
bwm 2
000261 -- ccmov= sec
006305 -- iut= asl r5
wr0 177776 -- r0=177776
wr1 000007 -- r1=7
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
cres
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area (Note: V = N xor C !)
brm 14
d=000004 -- ! asl 000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000000 -- ! asl 000001 -> n0z0v0c0; 000002
d=000002 -- !
d=000007 -- ! asl 100000 -> n0z1v1c1; 000000
d=000000 -- !
d=000000 -- ! asl 000100 -> n0z0v0c0; 000200
d=000200 -- !
d=000000 -- ! asl 000101 -> n0z0v0c0; 000202
d=000202 -- !
d=000012 -- ! asl 040100 -> n1z0v1c0; 100200
d=100200 -- !
d=000003 -- ! asl 100100 -> n0z0v1c1; 000200
d=000200 -- !
#--------
C Exec test 46.12wrc0: MOV - reg, C=0
#
wal 036000 -- setup test vector: for mov
bwm 6
000000 -- mov 000000,000000
000000 --
000001 -- mov 000001,000000
000000 --
100000 -- mov 100000,000000
000000 --
wal 013246 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
010405 -- iut= mov r4,r5
wr0 177776 -- r0=177776
wr1 000003 -- r1=3
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
cres
stapc 013240 -- start @ 13240 (2op reg)
wtgo
rpc d=013262 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 6
d=000004 -- ! mov 000000,000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000000 -- ! mov 000001,000000 -> n0z0v0c0; 000001
d=000001 -- !
d=000010 -- ! mov 100000,000000 -> n1z0v0c0; 100000
d=100000 -- !
#--------
C Exec test 46.12wrc1: MOV - reg, C=1
#
wal 013246 -- setup test instructions:
bwm 2
000261 -- ccmov= sec
010405 -- iut= mov r4,r5
wr0 177776 -- r0=177776
wr1 000003 -- r1=3
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
cres
stapc 013240 -- start @ 13240 (2op reg)
wtgo
rpc d=013262 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 6
d=000005 -- ! mov 000000,000000 -> n0z1v0c1; 000000
d=000000 -- !
d=000001 -- ! mov 000001,000000 -> n0z0v0c1; 000001
d=000001 -- !
d=000011 -- ! mov 100000,000000 -> n1z0v0c1; 100000
d=100000 -- !
#--------
C Exec test 46.12mc0: MOV - mem, C=0
#
wal 013276 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
011415 -- iut= mov (r4),(r5)
wr0 177776 -- r0=177776
wr1 000003 -- r1=3
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 001400 -- r4=1400
wr5 001402 -- r5=1402
wsp 001400 -- sp=1400
cres
stapc 013270 -- start @ 13270 (2op mem)
wtgo
rpc d=013312 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 6
d=000004 -- ! mov 000000,000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000000 -- ! mov 000001,000000 -> n0z0v0c0; 000001
d=000001 -- !
d=000010 -- ! mov 100000,000000 -> n1z0v0c0; 100000
d=100000 -- !
#--------
C Exec test 46.13wrc0: BIT - reg, C=0
#
wal 036000 -- setup test vector: for bit,bic,bis,xor
bwm 12
000000 -- bit 000000,000000
000000 --
000011 -- bit 000011,000000
000000 --
000011 -- bit 000011,000110
000110 --
000011 -- bit 000011,001100
001100 --
110000 -- bit 110000,011000
011000 --
110000 -- bit 110000,110000
110000 --
wal 013246 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
030405 -- iut= bit r4,r5
wr0 177776 -- r0=177776
wr1 000006 -- r1=6
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
cres
stapc 013240 -- start @ 13240 (2op reg)
wtgo
rpc d=013262 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 12
d=000004 -- ! bit 000000,000000 -> n0z1v0c0; (000000)
d=000000 -- !
d=000004 -- ! bit 000011,000000 -> n0z1v0c0; (000000)
d=000000 -- !
d=000000 -- ! bit 000011,000110 -> n0z0v0c0; (000010)
d=000110 -- !
d=000004 -- ! bit 000011,001100 -> n0z1v0c0; (000000)
d=001100 -- !
d=000000 -- ! bit 110000,011000 -> n0z0v0c0; (010000)
d=011000 -- !
d=000010 -- ! bit 110000,110000 -> n1z0v0c0; (100000)
d=110000 -- !
#--------
C Exec test 46.13wrc1: BIT - reg, C=1
#
wal 013246 -- setup test instructions:
bwm 2
000261 -- ccmov= sec
030405 -- iut= bit r4,r5
wr0 177776 -- r0=177776
wr1 000006 -- r1=6
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
cres
stapc 013240 -- start @ 13240 (2op reg)
wtgo
rpc d=013262 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 12
d=000005 -- ! bit 000000,000000 -> n0z1v0c1; (000000)
d=000000 -- !
d=000005 -- ! bit 000011,000000 -> n0z1v0c1; (000000)
d=000000 -- !
d=000001 -- ! bit 000011,000110 -> n0z0v0c1; (000010)
d=000110 -- !
d=000005 -- ! bit 000011,001100 -> n0z1v0c1; (000000)
d=001100 -- !
d=000001 -- ! bit 110000,011000 -> n0z0v0c1; (010000)
d=011000 -- !
d=000011 -- ! bit 110000,110000 -> n1z0v0c1; (100000)
d=110000 -- !
#--------
C Exec test 46.13wmc0: BIT - mem, C=0
#
wal 013276 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
031415 -- iut= bit (r4),(r5)
wr0 177776 -- r0=177776
wr1 000006 -- r1=6
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 001400 -- r4=1400
wr5 001402 -- r5=1402
wsp 001400 -- sp=1400
cres
stapc 013270 -- start @ 13270 (2op mem)
wtgo
rpc d=013312 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 12
d=000004 -- ! bit 000000,000000 -> n0z1v0c0; (000000)
d=000000 -- !
d=000004 -- ! bit 000011,000000 -> n0z1v0c0; (000000)
d=000000 -- !
d=000000 -- ! bit 000011,000110 -> n0z0v0c0; (000010)
d=000110 -- !
d=000004 -- ! bit 000011,001100 -> n0z1v0c0; (000000)
d=001100 -- !
d=000000 -- ! bit 110000,011000 -> n0z0v0c0; (010000)
d=011000 -- !
d=000010 -- ! bit 110000,110000 -> n1z0v0c0; (100000)
d=110000 -- !
#--------
C Exec test 46.14wrc0: BIC - reg, C=0
#
wal 013246 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
040405 -- iut= bic r4,r5
wr0 177776 -- r0=177776
wr1 000006 -- r1=6
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
cres
stapc 013240 -- start @ 13240 (2op reg)
wtgo
rpc d=013262 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 12
d=000004 -- ! bic 000000,000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000004 -- ! bic 000011,000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000000 -- ! bic 000011,000110 -> n0z0v0c0; 000100
d=000100 -- !
d=000000 -- ! bic 000011,001100 -> n0z0v0c0; 001100
d=001100 -- !
d=000000 -- ! bic 110000,011000 -> n0z0v0c0; 001000
d=001000 -- !
d=000004 -- ! bic 110000,110000 -> n0z1v0c0; 000000
d=000000 -- !
#--------
C Exec test 46.14wrc1: BIC - reg, C=1
#
wal 013246 -- setup test instructions:
bwm 2
000261 -- ccmov= sec
040405 -- iut= bic r4,r5
wr0 177776 -- r0=177776
wr1 000006 -- r1=6
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
cres
stapc 013240 -- start @ 13240 (2op reg)
wtgo
rpc d=013262 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 12
d=000005 -- ! bic 000000,000000 -> n0z1v0c1; 000000
d=000000 -- !
d=000005 -- ! bic 000011,000000 -> n0z1v0c1; 000000
d=000000 -- !
d=000001 -- ! bic 000011,000110 -> n0z0v0c1; 000100
d=000100 -- !
d=000001 -- ! bic 000011,001100 -> n0z0v0c1; 001100
d=001100 -- !
d=000001 -- ! bic 110000,011000 -> n0z0v0c1; 001000
d=001000 -- !
d=000005 -- ! bic 110000,110000 -> n0z1v0c1; 000000
d=000000 -- !
#--------
C Exec test 46.14wrc0: BIC - mem, C=0
#
wal 013276 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
041415 -- iut= bic (r4),(r5)
wr0 177776 -- r0=177776
wr1 000006 -- r1=6
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 001400 -- r4=1400
wr5 001402 -- r5=1402
wsp 001400 -- sp=1400
cres
stapc 013270 -- start @ 13270 (2op mem)
wtgo
rpc d=013312 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 12
d=000004 -- ! bic 000000,000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000004 -- ! bic 000011,000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000000 -- ! bic 000011,000110 -> n0z0v0c0; 000100
d=000100 -- !
d=000000 -- ! bic 000011,001100 -> n0z0v0c0; 001100
d=001100 -- !
d=000000 -- ! bic 110000,011000 -> n0z0v0c0; 001000
d=001000 -- !
d=000004 -- ! bic 110000,110000 -> n0z1v0c0; 000000
d=000000 -- !
#--------
C Exec test 46.15wrc0: BIS - reg, C=0
#
wal 013246 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
050405 -- iut= bis r4,r5
wr0 177776 -- r0=177776
wr1 000006 -- r1=6
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
cres
stapc 013240 -- start @ 13240 (2op reg)
wtgo
rpc d=013262 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 12
d=000004 -- ! bis 000000,000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000000 -- ! bis 000011,000000 -> n0z0v0c0; 000011
d=000011 -- !
d=000000 -- ! bis 000011,000110 -> n0z0v0c0; 000111
d=000111 -- !
d=000000 -- ! bis 000011,001100 -> n0z0v0c0; 001111
d=001111 -- !
d=000010 -- ! bis 110000,011000 -> n1z0v0c0; 111000
d=111000 -- !
d=000010 -- ! bis 110000,110000 -> n1z0v0c0; 110000
d=110000 -- !
#--------
C Exec test 46.15wrc1: BIS - reg, C=1
#
wal 013246 -- setup test instructions:
bwm 2
000261 -- ccmov= sec
050405 -- iut= bis r4,r5
wr0 177776 -- r0=177776
wr1 000006 -- r1=6
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
cres
stapc 013240 -- start @ 13240 (2op reg)
wtgo
rpc d=013262 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 12
d=000005 -- ! bis 000000,000000 -> n0z1v0c1; 000000
d=000000 -- !
d=000001 -- ! bis 000011,000000 -> n0z0v0c1; 000011
d=000011 -- !
d=000001 -- ! bis 000011,000110 -> n0z0v0c1; 000111
d=000111 -- !
d=000001 -- ! bis 000011,001100 -> n0z0v0c1; 001111
d=001111 -- !
d=000011 -- ! bis 110000,011000 -> n1z0v0c1; 111000
d=111000 -- !
d=000011 -- ! bis 110000,110000 -> n1z0v0c1; 110000
d=110000 -- !
#--------
C Exec test 46.16wrc0: XOR - reg, C=0
#
wal 013246 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
074405 -- iut= xor r4,r5
wr0 177776 -- r0=177776
wr1 000006 -- r1=6
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
cres
stapc 013240 -- start @ 13240 (2op reg)
wtgo
rpc d=013262 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 12
d=000004 -- ! xor 000000,000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000000 -- ! xor 000011,000000 -> n0z0v0c0; 000011
d=000011 -- !
d=000000 -- ! xor 000011,000110 -> n0z0v0c0; 000101
d=000101 -- !
d=000000 -- ! xor 000011,001100 -> n0z0v0c0; 001111
d=001111 -- !
d=000010 -- ! xor 110000,011000 -> n1z0v0c0; 101000
d=101000 -- !
d=000004 -- ! xor 110000,110000 -> n1z0v0c0; 000000
d=000000 -- !
#--------
C Exec test 46.16wrc1: XOR - reg, C=1
#
wal 013246 -- setup test instructions:
bwm 2
000261 -- ccmov= sec
074405 -- iut= xor r4,r5
wr0 177776 -- r0=177776
wr1 000006 -- r1=6
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
cres
stapc 013240 -- start @ 13240 (2op reg)
wtgo
rpc d=013262 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 12
d=000005 -- ! xor 000000,000000 -> n0z1v0c1; 000000
d=000000 -- !
d=000001 -- ! xor 000011,000000 -> n0z0v0c1; 000011
d=000011 -- !
d=000001 -- ! xor 000011,000110 -> n0z0v0c1; 000101
d=000101 -- !
d=000001 -- ! xor 000011,001100 -> n0z0v0c1; 001111
d=001111 -- !
d=000011 -- ! xor 110000,011000 -> n1z0v0c1; 101000
d=101000 -- !
d=000005 -- ! xor 110000,110000 -> n1z0v0c1; 000000
d=000000 -- !
#--------
C Exec test 46.17wr: CMP - reg
#
wal 036000 -- setup test vector: for cmp,add,sub
bwm 38
000000 -- cmp 000000,000000
000000 --
000001 -- cmp 000001,000000
000000 --
177777 -- cmp 177777,000000
000000 --
000000 -- cmp 000000,000001
000001 --
000001 -- cmp 000001,000001
000001 --
177777 -- cmp 177777,000001
000001 --
077776 -- cmp 077776,077777
077777 --
077777 -- cmp 077777,077777
077777 --
100000 -- cmp 100000,077777
077777 --
000001 -- cmp 000001,077777
077777 --
177777 -- cmp 177777,077777
077777 --
077777 -- cmp 077777,100000
100000 --
100000 -- cmp 100000,100000
100000 --
100001 -- cmp 100001,100000
100000 --
000001 -- cmp 000001,100000
100000 --
177777 -- cmp 177777,100000
100000 --
000000 -- cmp 000000,177777
177777 --
000001 -- cmp 000001,177777
177777 --
177777 -- cmp 177777,177777
177777 --
wal 013246 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
020405 -- iut= cmp r4,r5
wr0 177776 -- r0=177776
wr1 000023 -- r1=23 (19.)
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
cres
stapc 013240 -- start @ 13240 (2op reg)
wtgo
rpc d=013262 -- ! pc=halt
rr1 d=000000 -- ! r1=0 (Note: C=1 if dst > src unsigned)
wal 037000 -- check result area (Note: V=1 if s xor d and r eq d)
brm 38
d=000004 -- ! cmp 000000,000000 -> n0z1v0c0; (000000)
d=000000 -- !
d=000000 -- ! cmp 000001,000000 -> n0z0v0c0; (000001)
d=000000 -- !
d=000010 -- ! cmp 177777,000000 -> n1z0v0c0; (177777)
d=000000 -- !
d=000011 -- ! cmp 000000,000001 -> n1z0v0c1; (177777+C)
d=000001 -- !
d=000004 -- ! cmp 000001,000001 -> n0z1v0c0; (000000)
d=000001 -- !
d=000010 -- ! cmp 177777,000001 -> n1z0v0c0; (177776)
d=000001 -- !
d=000011 -- ! cmp 077776,077777 -> n1z0v0c1; (177777+C)
d=077777 -- !
d=000004 -- ! cmp 077777,077777 -> n0z1v0c0; (000000)
d=077777 -- !
d=000002 -- ! cmp 100000,077777 -> n0z0v1c0; (000001)
d=077777 -- !
d=000011 -- ! cmp 000001,077777 -> n1z0v0c1; (100002+C)
d=077777 -- !
d=000010 -- ! cmp 177777,077777 -> n1z0v0c0; (100000)
d=077777 -- !
d=000013 -- ! cmp 077777,100000 -> n1z0v1c1; (177777+C)
d=100000 -- !
d=000004 -- ! cmp 100000,100000 -> n0z1v0c0; (000000)
d=100000 -- !
d=000000 -- ! cmp 100001,100000 -> n0z0v0c0; (000001)
d=100000 -- !
d=000013 -- ! cmp 000001,100000 -> n1z0v1c1; (100001+C)
d=100000 -- !
d=000000 -- ! cmp 177777,100000 -> n0z0v0c0; (077777)
d=100000 -- !
d=000001 -- ! cmp 000000,177777 -> n0z0v0c1; (000001+C)
d=177777 -- !
d=000001 -- ! cmp 000001,177777 -> n0z0v0c1; (000002+C)
d=177777 -- !
d=000004 -- ! cmp 177777,177777 -> n0z1v0c0; (000000)
d=177777 -- !
#--------
C Exec test 46.18r: ADD - reg
#
wal 013246 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
060405 -- iut= add r4,r5
wr0 177776 -- r0=177776
wr1 000023 -- r1=23 (19.)
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
cres
stapc 013240 -- start @ 13240 (2op reg)
wtgo
rpc d=013262 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area (Note: V=1 if s eq d and r neq d)
brm 38
d=000004 -- ! add 000000,000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000000 -- ! add 000001,000000 -> n0z0v0c0; 000001
d=000001 -- !
d=000010 -- ! add 177777,000000 -> n1z0v0c0; 177777
d=177777 -- !
d=000000 -- ! add 000000,000001 -> n0z0v0c0; 000001
d=000001 -- !
d=000000 -- ! add 000001,000001 -> n0z0v0c0; 000002
d=000002 -- !
d=000005 -- ! add 177777,000001 -> n0z1v0c1; 000000+C
d=000000 -- !
d=000012 -- ! add 077776,077777 -> n1z0v1c0; 177775
d=177775 -- !
d=000012 -- ! add 077777,077777 -> n1z0v1c0; 177776
d=177776 -- !
d=000010 -- ! add 100000,077777 -> n1z0v0c0; 177777
d=177777 -- !
d=000012 -- ! add 000001,077777 -> n1z0v1c0; 100000
d=100000 -- !
d=000001 -- ! add 177777,077777 -> n0z0v0c1; 077776+C
d=077776 -- !
d=000010 -- ! add 077777,100000 -> n1z0v0c1; 177777+C
d=177777 -- !
d=000007 -- ! add 100000,100000 -> n0z1v1c1; 000000+C
d=000000 -- !
d=000003 -- ! add 100001,100000 -> n0z0v1c1; 000001+C
d=000001 -- !
d=000010 -- ! add 000001,100000 -> n1z0v0c0; 100001
d=100001 -- !
d=000003 -- ! add 177777,100000 -> n0z0v1c1; 077777+C
d=077777 -- !
d=000010 -- ! add 000000,177777 -> n1z0v0c0; 177777
d=177777 -- !
d=000005 -- ! add 000001,177777 -> n0z1v0c1; 000000+C
d=000000 -- !
d=000011 -- ! add 177777,177777 -> n1z0v0c1; 177776+C
d=177776 -- !
#--------
C Exec test 46.19r: SUB - reg
#
wal 013246 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
160405 -- iut= sub r4,r5
wr0 177776 -- r0=177776
wr1 000023 -- r1=23 (19.)
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
cres
stapc 013240 -- start @ 13240 (2op reg)
wtgo
rpc d=013262 -- ! pc=halt
rr1 d=000000 -- ! r1=0 (Note: C=1 if src > dst unsigned)
wal 037000 -- check result area (Note: V=1 if s xor d and r eq s)
brm 38
d=000004 -- ! sub 000000,000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000011 -- ! sub 000001,000000 -> n1z0v0c1; 177777+C
d=177777 -- !
d=000001 -- ! sub 177777,000000 -> n0z0v0c1; 000001+C
d=000001 -- !
d=000000 -- ! sub 000000,000001 -> n0z0v0c0; 000001
d=000001 -- !
d=000004 -- ! sub 000001,000001 -> n0z1v0c0; 000000
d=000000 -- !
d=000001 -- ! sub 177777,000001 -> n0z0v0c1; 000002+C
d=000002 -- !
d=000000 -- ! sub 077776,077777 -> n0z0v0c0; 000001
d=000001 -- !
d=000004 -- ! sub 077777,077777 -> n0z1v0c0; 000000
d=000000 -- !
d=000013 -- ! sub 100000,077777 -> n1z0v1c1; 177777+C
d=177777 -- !
d=000000 -- ! sub 000001,077777 -> n0z0v0c0; 077776
d=077776 -- !
d=000013 -- ! sub 177777,077777 -> n1z0v1c1; 100000+C
d=100000 -- !
d=000002 -- ! sub 077777,100000 -> n0z0v1c0; 000001
d=000001 -- !
d=000004 -- ! sub 100000,100000 -> n0z1v0c0; 000000
d=000000 -- !
d=000011 -- ! sub 100001,100000 -> n1z0v0c1; 177777+C
d=177777 -- !
d=000002 -- ! sub 000001,100000 -> n0z0v1c0; 077777
d=077777 -- !
d=000011 -- ! sub 177777,100000 -> n1z0v0c1: 100001+C
d=100001 -- !
d=000010 -- ! sub 000000,177777 -> n1z0v0c0; 177777
d=177777 -- !
d=000010 -- ! sub 000001,177777 -> n1z0v0c0; 177776
d=177776 -- !
d=000004 -- ! sub 177777,177777 -> n0z1v0c0; 000000
d=000000 -- !
#
C Exec test 46.20r: SWAP - reg
#
wal 036000 -- setup test vector: for swap
bwm 9
000000 -- swap 000000
000001 -- swap 000001
000200 -- swap 000200
000400 -- swap 000400
100000 -- swap 100000
000401 -- swap 000401
000600 -- swap 000600
100001 -- swap 100001
100200 -- swap 100200
wal 013204 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
000305 -- iut= swap r5
wr0 177776 -- r0=177776
wr1 000011 -- r1=11 (9.)
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
cres
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area (Note: N,Z from lsb of result)
brm 18
d=000004 -- ! swap 000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000004 -- ! swap 000001 -> n0z1v0c0; 000400
d=000400 -- !
d=000004 -- ! swap 000200 -> n0z1v0c0; 100000
d=100000 -- !
d=000000 -- ! swap 000400 -> n0z0v0c0; 000001
d=000001 -- !
d=000010 -- ! swap 100000 -> n1z0v0c0; 000200
d=000200 -- !
d=000000 -- ! swap 000401 -> n0z0v0c0; 000401
d=000401 -- !
d=000000 -- ! swap 000600 -> n0z0v0c0; 100001
d=100001 -- !
d=000010 -- ! swap 100001 -> n1z0v0c0; 000600
d=000600 -- !
d=000010 -- ! swap 100200 -> n1z0v0c0; 100200
d=100200 -- !
#--------
C Exec code 46 pass 2 (systematic result+cc test of 1+2op instructions; byte)
C Exec test 46.1br: COMB - reg
#
wal 036000 -- setup test vector: for com,inc,dec,neg,adc,sbc,tst (b)
bwm 5
000000 -- comb 000000
000001 -- comb 000001
000177 -- comb 000177
000200 -- comb 000200
000377 -- comb 000377
wal 013204 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
105105 -- iut= comb r5
wr0 177776 -- r0=177776
wr1 000005 -- r1=5
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
cres
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 10
d=000011 -- ! comb 000000 -> n1z0v0c1; 000377
d=000377 -- !
d=000011 -- ! comb 000001 -> n1z0v0c1; 000376
d=000376 -- !
d=000011 -- ! comb 000177 -> n1z0v0c1; 000200
d=000200 -- !
d=000001 -- ! comb 000200 -> n0z0v0c1; 000177
d=000177 -- !
d=000005 -- ! comb 000377 -> n0z1v0c1; 000000
d=000000 -- !
#--------
C Exec test 46.1bm: COMB - mem
#
wal 013224 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
105115 -- iut= comb (r5)
wr0 177776 -- r0=177776
wr1 000005 -- r1=5
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 001400 -- r4=1400
wr5 001402 -- r5=1402
wsp 001400 -- sp=1400
cres
stapc 013220 -- start @ 13220 (1op mem)
wtgo
rpc d=013240 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 10
d=000011 -- ! comb 000000 -> n1z0v0c1; 000377
d=000377 -- !
d=000011 -- ! comb 000001 -> n1z0v0c1; 000376
d=000376 -- !
d=000011 -- ! comb 000177 -> n1z0v0c1; 000200
d=000200 -- !
d=000001 -- ! comb 000200 -> n0z0v0c1; 000177
d=000177 -- !
d=000005 -- ! comb 000377 -> n0z1v0c1; 000000
d=000000 -- !
#--------
C Exec test 46.2brc0: INCB - reg,C=0
#
wal 013204 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
105205 -- iut= incb r5
wr0 177776 -- r0=177776
wr1 000005 -- r1=5
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
cres
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 10
d=000000 -- ! incb 000000 -> n0z0v0c0; 000001
d=000001 -- !
d=000000 -- ! incb 000001 -> n0z0v0c0; 000002
d=000002 -- !
d=000012 -- ! incb 000177 -> n1z0v1c0; 000200
d=000200 -- !
d=000010 -- ! incb 000200 -> n1z0v0c0; 000201
d=000201 -- !
d=000004 -- ! incb 000377 -> n0z1v0c0; 000000
d=000000 -- !
#--------
C Exec test 46.2brc1: INCB - reg,C=1
#
wal 013204 -- setup test instructions:
bwm 2
000261 -- ccmov= sec
105205 -- iut= incb r5
wr0 177776 -- r0=177776
wr1 000005 -- r1=5
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
cres
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 10
d=000001 -- ! incb 000000 -> n0z0v0c1; 000001
d=000001 -- !
d=000001 -- ! incb 000001 -> n0z0v0c1; 000002
d=000002 -- !
d=000013 -- ! incb 000177 -> n1z0v1c1; 000200
d=000200 -- !
d=000011 -- ! incb 000200 -> n1z0v0c1; 000201
d=000201 -- !
d=000005 -- ! incb 000377 -> n0z1v0c1; 000000
d=000000 -- !
#--------
C Exec test 46.3brc0: DECB - reg,C=0
#
wal 013204 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
105305 -- iut= decb r5
wr0 177776 -- r0=177776
wr1 000005 -- r1=5
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
cres
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 10
d=000010 -- ! decb 000000 -> n1z0v0c0; 000377
d=000377 -- !
d=000004 -- ! decb 000001 -> n0z1v0c0; 000000
d=000000 -- !
d=000000 -- ! decb 000177 -> n0z0v0c0; 000176
d=000176 -- !
d=000002 -- ! decb 000200 -> n0z0v1c0; 000177
d=000177 -- !
d=000010 -- ! decb 000377 -> n1z0v0c0; 000376
d=000376 -- !
#--------
C Exec test 46.3brc1: DECB - reg,C=1
#
wal 013204 -- setup test instructions:
bwm 2
000261 -- ccmov= sec
105305 -- iut= decb r5
wr0 177776 -- r0=177776
wr1 000005 -- r1=5
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
cres
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 10
d=000011 -- ! decb 000000 -> n1z0v0c1; 000377
d=000377 -- !
d=000005 -- ! decb 000001 -> n0z1v0c1; 000000
d=000000 -- !
d=000001 -- ! decb 000177 -> n0z0v0c1; 000176
d=000176 -- !
d=000003 -- ! decb 000200 -> n0z0v1c1; 000177
d=000177 -- !
d=000011 -- ! decb 000377 -> n1z0v0c1; 000376
d=000376 -- !
#--------
C Exec test 46.4br: NEGB - reg
#
wal 013204 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
105405 -- iut= negb r5
wr0 177776 -- r0=177776
wr1 000005 -- r1=5
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
cres
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 10
d=000004 -- ! negb 000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000011 -- ! negb 000001 -> n1z0v0c1; 000377
d=000377 -- !
d=000011 -- ! negb 000177 -> n1z0v0c1; 000201
d=000201 -- !
d=000013 -- ! negb 000200 -> n1z0v1c1; 000200
d=000200 -- !
d=000001 -- ! negb 000377 -> n0z0v0c1; 000001
d=000001 -- !
#--------
C Exec test 46.5brc0: ADCB - reg,C=0
#
wal 013204 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
105505 -- iut= adcb r5
wr0 177776 -- r0=177776
wr1 000005 -- r1=5
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
cres
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 10
d=000004 -- ! adcb 000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000000 -- ! adcb 000001 -> n0z0v0c0; 000001
d=000001 -- !
d=000000 -- ! adcb 000177 -> n0z0v0c0; 000177
d=000177 -- !
d=000010 -- ! adcb 000200 -> n1z0v0c0; 000200
d=000200 -- !
d=000010 -- ! adcb 000377 -> n1z0v0c0; 000377
d=000377 -- !
#--------
C Exec test 46.5brc1: ADCB - reg,C=1
#
wal 013204 -- setup test instructions:
bwm 2
000261 -- ccmov= sec
105505 -- iut= adcb r5
wr0 177776 -- r0=177776
wr1 000005 -- r1=5
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
cres
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 10
d=000000 -- ! adcb 000000 -> n0z0v0c0; 000001
d=000001 -- !
d=000000 -- ! adcb 000001 -> n0z0v0c0; 000002
d=000002 -- !
d=000012 -- ! adcb 000177 -> n1z0v1c0; 000200
d=000200 -- !
d=000010 -- ! adcb 000200 -> n1z0v0c0; 000201
d=000201 -- !
d=000005 -- ! adcb 000377 -> n0z1v0c1; 000000
d=000000 -- !
#--------
C Exec test 46.6brc0: SBCB - reg,C=0
#
wal 013204 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
105605 -- iut= sbcb r5
wr0 177776 -- r0=177776
wr1 000005 -- r1=5
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
cres
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 10
d=000004 -- ! sbcb 000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000000 -- ! sbcb 000001 -> n0z0v0c0; 000001
d=000001 -- !
d=000000 -- ! sbcb 000177 -> n0z0v0c0; 000177
d=000177 -- !
d=000010 -- ! sbcb 000200 -> n1z0v0c0; 000200
d=000200 -- !
d=000010 -- ! sbcb 000377 -> n1z0v0c0; 000377
d=000377 -- !
#--------
C Exec test 46.6brc1: SBCB - reg,C=1
#
wal 013204 -- setup test instructions:
bwm 2
000261 -- ccmov= sec
105605 -- iut= sbcb r5
wr0 177776 -- r0=177776
wr1 000005 -- r1=5
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
cres
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 10
d=000011 -- ! sbcb 000000 -> n1z0v0c1; 000377
d=000377 -- !
d=000004 -- ! sbcb 000001 -> n0z1v0c0; 000000
d=000000 -- !
d=000000 -- ! sbcb 000177 -> n0z0v0c0; 000176
d=000176 -- !
d=000002 -- ! sbcb 000200 -> n0z0v1c0; 000177
d=000177 -- !
d=000010 -- ! sbcb 000377 -> n1z0v0c0; 000376
d=000376 -- !
#--------
C Exec test 46.7br: TSTB - reg
#
wal 013204 -- setup test instructions:
bwm 2
000261 -- ccmov= sec
105705 -- iut= tstb r5
wr0 177776 -- r0=177776
wr1 000005 -- r1=5
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
cres
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 10
d=000004 -- ! tstb 000000 -> n0z1v0c0;
d=000000 -- !
d=000000 -- ! tstb 000001 -> n0z0v0c0;
d=000001 -- !
d=000000 -- ! tstb 000177 -> n0z0v0c0;
d=000177 -- !
d=000010 -- ! tstb 000200 -> n1z0v0c0;
d=000200 -- !
d=000010 -- ! tstb 000377 -> n1z0v0c0;
d=000377 -- !
#--------
C Exec test 46.7bm: TSTB - mem
#
wal 013224 -- setup test instructions:
bwm 2
000261 -- ccmov= sec
105715 -- iut= tstb (r5)
wr0 177776 -- r0=177776
wr1 000005 -- r1=5
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 001400 -- r4=1400
wr5 001402 -- r5=1402
wsp 001400 -- sp=1400
cres
stapc 013220 -- start @ 13220 (1op mem)
wtgo
rpc d=013240 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 10
d=000004 -- ! tstb 000000 -> n0z1v0c0;
d=000000 -- !
d=000000 -- ! tstb 000001 -> n0z0v0c0;
d=000001 -- !
d=000000 -- ! tstb 000177 -> n0z0v0c0;
d=000177 -- !
d=000010 -- ! tstb 000200 -> n1z0v0c0;
d=000200 -- !
d=000010 -- ! tstb 000377 -> n1z0v0c0;
d=000377 -- !
#--------
C Exec test 46.8brc0: RORB - reg, C=0
#
wal 036000 -- setup test vector: for ror,rol,ars,asl (b)
bwm 7
000000 -- ror 000000
000001 -- ror 000001
000200 -- ror 000200
000010 -- ror 000010
000011 -- ror 000011
000110 -- ror 000110
000210 -- ror 000210
wal 013204 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
106005 -- iut= rorb r5
wr0 177776 -- r0=177776
wr1 000007 -- r1=7
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
cres
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area (Note: V = N xor C !)
brm 14
d=000004 -- ! rorb 000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000007 -- ! rorb 000001 -> n0z1v1c1; 000000
d=000000 -- !
d=000000 -- ! rorb 000200 -> n0z0v0c0; 000100
d=000100 -- !
d=000000 -- ! rorb 000010 -> n0z0v0c0; 000004
d=000004 -- !
d=000003 -- ! rorb 000011 -> n0z0v1c1; 000004
d=000004 -- !
d=000000 -- ! rorb 000110 -> n0z0v0c0; 000044
d=000044 -- !
d=000000 -- ! rorb 000210 -> n0z0v0c0; 000104
d=000104 -- !
#--------
C Exec test 46.8brc1: RORB - reg, C=1
#
wal 013204 -- setup test instructions:
bwm 2
000261 -- ccmov= sec
106005 -- iut= rorb r5
wr0 177776 -- r0=177776
wr1 000007 -- r1=7
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
cres
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area (Note: V = N xor C !)
brm 14
d=000012 -- ! rorb 000000 -> n1z0v1c0; 000200
d=000200 -- !
d=000011 -- ! rorb 000001 -> n1z0v0c1; 000200
d=000200 -- !
d=000012 -- ! rorb 000200 -> n1z0v1c0; 000300
d=000300 -- !
d=000012 -- ! rorb 000010 -> n1z0v1c0; 000204
d=000204 -- !
d=000011 -- ! rorb 000011 -> n1z0v0c1; 000204
d=000204 -- !
d=000012 -- ! rorb 000110 -> n1z0v1c0; 000244
d=000244 -- !
d=000012 -- ! rorb 000210 -> n1z0v1c0; 000304
d=000304 -- !
#--------
C Exec test 46.9brc0: ROLB - reg, C=0
#
wal 013204 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
106105 -- iut= rolb r5
wr0 177776 -- r0=177776
wr1 000007 -- r1=7
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
cres
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area (Note: V = N xor C !)
brm 14
d=000004 -- ! rolb 000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000000 -- ! rolb 000001 -> n0z0v0c0; 000002
d=000002 -- !
d=000007 -- ! rolb 000200 -> n0z1v1c1; 000000
d=000000 -- !
d=000000 -- ! rolb 000010 -> n0z0v0c0; 000020
d=000020 -- !
d=000000 -- ! rolb 000011 -> n0z0v0c0; 000022
d=000022 -- !
d=000012 -- ! rolb 000110 -> n1z0v1c0; 000220
d=000220 -- !
d=000003 -- ! rolb 000210 -> n0z0v1c1; 000020
d=000020 -- !
#--------
C Exec test 46.9brc1: ROLB - reg, C=1
#
wal 013204 -- setup test instructions:
bwm 2
000261 -- ccmov= sec
106105 -- iut= rolb r5
wr0 177776 -- r0=177776
wr1 000007 -- r1=7
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
cres
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area (Note: V = N xor C !)
brm 14
d=000000 -- ! rolb 000000 -> n0z0v0c0; 000001
d=000001 -- !
d=000000 -- ! rolb 000001 -> n0z0v0c0; 000003
d=000003 -- !
d=000003 -- ! rolb 000200 -> n0z0v1c1; 000001
d=000001 -- !
d=000000 -- ! rolb 000010 -> n0z0v0c0; 000021
d=000021 -- !
d=000000 -- ! rolb 000011 -> n0z0v0c0; 000023
d=000023 -- !
d=000012 -- ! rolb 000110 -> n1z0v1c0; 000221
d=000221 -- !
d=000003 -- ! rolb 000210 -> n0z0v1c1; 000021
d=000021 -- !
#--------
C Exec test 46.10brc0: ASRB - reg, C=0
#
wal 013204 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
106205 -- iut= asrb r5
wr0 177776 -- r0=177776
wr1 000007 -- r1=7
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
cres
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area (Note: V = N xor C !)
brm 14
d=000004 -- ! asrb 000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000007 -- ! asrb 000001 -> n0z1v1c1; 000000
d=000000 -- !
d=000012 -- ! asrb 000200 -> n1z0v1c0; 000300
d=000300 -- !
d=000000 -- ! asrb 000010 -> n0z0v0c0; 000004
d=000004 -- !
d=000003 -- ! asrb 000011 -> n0z0v1c1; 000004
d=000004 -- !
d=000000 -- ! asrb 000110 -> n0z0v0c0; 000044
d=000044 -- !
d=000012 -- ! asrb 000210 -> n1z0v1c0; 000304
d=000304 -- !
#--------
C Exec test 46.10brc1: ASRB - reg, C=1
#
wal 013204 -- setup test instructions:
bwm 2
000261 -- ccmov= sec
106205 -- iut= asrb r5
wr0 177776 -- r0=177776
wr1 000007 -- r1=7
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
cres
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area (Note: V = N xor C !)
brm 14
d=000004 -- ! asrb 000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000007 -- ! asrb 000001 -> n0z1v1c1; 000000
d=000000 -- !
d=000012 -- ! asrb 000200 -> n1z0v1c0; 000300
d=000300 -- !
d=000000 -- ! asrb 000010 -> n0z0v0c0; 000004
d=000004 -- !
d=000003 -- ! asrb 000011 -> n0z0v1c1; 000004
d=000004 -- !
d=000000 -- ! asrb 000110 -> n0z0v0c0; 000044
d=000044 -- !
d=000012 -- ! asrb 000210 -> n1z0v1c0; 000304
d=000304 -- !
#--------
C Exec test 46.11brc0: ASLB - reg, C=0
#
wal 013204 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
106305 -- iut= aslb r5
wr0 177776 -- r0=177776
wr1 000007 -- r1=7
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
cres
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area (Note: V = N xor C !)
brm 14
d=000004 -- ! aslb 000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000000 -- ! aslb 000001 -> n0z0v0c0; 000002
d=000002 -- !
d=000007 -- ! aslb 000200 -> n0z1v1c1; 000000
d=000000 -- !
d=000000 -- ! aslb 000010 -> n0z0v0c0; 000020
d=000020 -- !
d=000000 -- ! aslb 000011 -> n0z0v0c0; 000022
d=000022 -- !
d=000012 -- ! aslb 000110 -> n1z0v1c0; 000220
d=000220 -- !
d=000003 -- ! aslb 000210 -> n0z0v1c1; 000020
d=000020 -- !
#--------
C Exec test 46.11brc1: ASLB - reg, C=1
#
wal 013204 -- setup test instructions:
bwm 2
000261 -- ccmov= sec
106305 -- iut= aslb r5
wr0 177776 -- r0=177776
wr1 000007 -- r1=7
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
cres
stapc 013200 -- start @ 13200 (1op reg)
wtgo
rpc d=013220 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area (Note: V = N xor C !)
brm 14
d=000004 -- ! aslb 000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000000 -- ! aslb 000001 -> n0z0v0c0; 000002
d=000002 -- !
d=000007 -- ! aslb 000200 -> n0z1v1c1; 000000
d=000000 -- !
d=000000 -- ! aslb 000010 -> n0z0v0c0; 000020
d=000020 -- !
d=000000 -- ! aslb 000011 -> n0z0v0c0; 000022
d=000022 -- !
d=000012 -- ! aslb 000110 -> n1z0v1c0; 000220
d=000220 -- !
d=000003 -- ! aslb 000210 -> n0z0v1c1; 000020
d=000020 -- !
#--------
C Exec test 46.12brc0: MOVB - reg, C=0
#
wal 036000 -- setup test vector: for mov
bwm 6
000000 -- movb 000000,000000
000000 --
000001 -- movb 000001,000000
000000 --
000200 -- movb 000200,000000
000000 --
wal 013246 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
110405 -- iut= movb r4,r5
wr0 177776 -- r0=177776
wr1 000003 -- r1=3
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
cres
stapc 013240 -- start @ 13240 (2op reg)
wtgo
rpc d=013262 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 6
d=000004 -- ! movb 000000,000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000000 -- ! movb 000001,000000 -> n0z0v0c0; 000001
d=000001 -- !
d=000010 -- ! movb 000200,000000 -> n1z0v0c0; 177600
d=177600 -- !
#--------
C Exec test 46.12brc1: MOVB - reg, C=1
#
wal 013246 -- setup test instructions:
bwm 2
000261 -- ccmov= sec
110405 -- iut= movb r4,r5
wr0 177776 -- r0=177776
wr1 000003 -- r1=3
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
cres
stapc 013240 -- start @ 13240 (2op reg)
wtgo
rpc d=013262 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 6
d=000005 -- ! movb 000000,000000 -> n0z1v0c1; 000000
d=000000 -- !
d=000001 -- ! movb 000001,000000 -> n0z0v0c1; 000001
d=000001 -- !
d=000011 -- ! movb 000200,000000 -> n1z0v0c1; 177600
d=177600 -- !
#--------
C Exec test 46.12bmc0: MOVB - mem, C=0
#
wal 013276 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
111415 -- iut= movb (r4),(r5)
wr0 177776 -- r0=177776
wr1 000003 -- r1=3
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 001400 -- r4=1400
wr5 001402 -- r5=1402
wsp 001400 -- sp=1400
cres
stapc 013270 -- start @ 13270 (2op mem)
wtgo
rpc d=013312 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 6
d=000004 -- ! movb 000000,000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000000 -- ! movb 000001,000000 -> n0z0v0c0; 000001
d=000001 -- !
d=000010 -- ! movb 000200,000000 -> n1z0v0c0; 000200
d=000200 -- !
#--------
C Exec test 46.13brc0: BITB - reg, C=0
#
wal 036000 -- setup test vector: for bit,bic,bis (b)
bwm 12
000000 -- bitb 000000,000000
000000 --
000003 -- bitb 000003,000000
000000 --
000003 -- bitb 000003,000006
000006 --
000003 -- bitb 000003,000014
000014 --
000300 -- bitb 000300,000140
000140 --
000300 -- bitb 000300,000300
000300 --
wal 013246 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
130405 -- iut= bitb r4,r5
wr0 177776 -- r0=177776
wr1 000006 -- r1=6
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
cres
stapc 013240 -- start @ 13240 (2op reg)
wtgo
rpc d=013262 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 12
d=000004 -- ! bitb 000000,000000 -> n0z1v0c0; (000000)
d=000000 -- !
d=000004 -- ! bitb 000003,000000 -> n0z1v0c0; (000000)
d=000000 -- !
d=000000 -- ! bitb 000003,000006 -> n0z0v0c0; (000002)
d=000006 -- !
d=000004 -- ! bitb 000003,000014 -> n0z1v0c0; (000000)
d=000014 -- !
d=000000 -- ! bitb 000300,000140 -> n0z0v0c0; (000100)
d=000140 -- !
d=000010 -- ! bitb 000300,000300 -> n1z0v0c0; (000300)
d=000300 -- !
#--------
C Exec test 46.13brc1: BITB - reg, C=1
#
wal 013246 -- setup test instructions:
bwm 2
000261 -- ccmov= sec
130405 -- iut= bitb r4,r5
wr0 177776 -- r0=177776
wr1 000006 -- r1=6
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
cres
stapc 013240 -- start @ 13240 (2op reg)
wtgo
rpc d=013262 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 12
d=000005 -- ! bitb 000000,000000 -> n0z1v0c1; (000000)
d=000000 -- !
d=000005 -- ! bitb 000003,000000 -> n0z1v0c1; (000000)
d=000000 -- !
d=000001 -- ! bitb 000003,000006 -> n0z0v0c1; (000002)
d=000006 -- !
d=000005 -- ! bitb 000003,000014 -> n0z1v0c1; (000000)
d=000014 -- !
d=000001 -- ! bitb 000300,000140 -> n0z0v0c1; (000100)
d=000140 -- !
d=000011 -- ! bitb 000300,000300 -> n1z0v0c1; (000300)
d=000300 -- !
#--------
C Exec test 46.13bmc0: BITB - mem, C=0
#
wal 013276 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
131415 -- iut= bitb (r4),(r5)
wr0 177776 -- r0=177776
wr1 000006 -- r1=6
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 001400 -- r4=1400
wr5 001402 -- r5=1402
wsp 001400 -- sp=1400
cres
stapc 013270 -- start @ 13270 (2op mem)
wtgo
rpc d=013312 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 12
d=000004 -- ! bitb 000000,000000 -> n0z1v0c0; (000000)
d=000000 -- !
d=000004 -- ! bitb 000003,000000 -> n0z1v0c0; (000000)
d=000000 -- !
d=000000 -- ! bitb 000003,000006 -> n0z0v0c0; (000002)
d=000006 -- !
d=000004 -- ! bitb 000003,000014 -> n0z1v0c0; (000000)
d=000014 -- !
d=000000 -- ! bitb 000300,000140 -> n0z0v0c0; (000100)
d=000140 -- !
d=000010 -- ! bitb 000300,000300 -> n1z0v0c0; (000300)
d=000300 -- !
#--------
C Exec test 46.14brc0: BICB - reg, C=0
#
wal 013246 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
140405 -- iut= bicb r4,r5
wr0 177776 -- r0=177776
wr1 000006 -- r1=6
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
cres
stapc 013240 -- start @ 13240 (2op reg)
wtgo
rpc d=013262 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 12
d=000004 -- ! bicb 000000,000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000004 -- ! bicb 000003,000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000000 -- ! bicb 000003,000006 -> n0z0v0c0; 000004
d=000004 -- !
d=000000 -- ! bicb 000003,000014 -> n0z0v0c0; 000014
d=000014 -- !
d=000000 -- ! bicb 000300,000140 -> n0z0v0c0; 000040
d=000040 -- !
d=000004 -- ! bicb 000300,000300 -> n0z1v0c0; 000000
d=000000 -- !
#--------
C Exec test 46.14brc1: BICB - reg, C=1
#
wal 013246 -- setup test instructions:
bwm 2
000261 -- ccmov= sec
140405 -- iut= bicb r4,r5
wr0 177776 -- r0=177776
wr1 000006 -- r1=6
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
cres
stapc 013240 -- start @ 13240 (2op reg)
wtgo
rpc d=013262 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 12
d=000005 -- ! bicb 000000,000000 -> n0z1v0c1; 000000
d=000000 -- !
d=000005 -- ! bicb 000003,000000 -> n0z1v0c1; 000000
d=000000 -- !
d=000001 -- ! bicb 000003,000006 -> n0z0v0c1; 000004
d=000004 -- !
d=000001 -- ! bicb 000003,000014 -> n0z0v0c1; 000014
d=000014 -- !
d=000001 -- ! bicb 000300,000140 -> n0z0v0c1; 000040
d=000040 -- !
d=000005 -- ! bicb 000300,000300 -> n0z1v0c1; 000000
d=000000 -- !
#--------
C Exec test 46.14bmrc0: BICB - mem, C=0
#
wal 013276 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
141415 -- iut= bicb (r4),(r5)
wr0 177776 -- r0=177776
wr1 000006 -- r1=6
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 001400 -- r4=1400
wr5 001402 -- r5=1402
wsp 001400 -- sp=1400
cres
stapc 013270 -- start @ 13270 (2op mem)
wtgo
rpc d=013312 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 12
d=000004 -- ! bicb 000000,000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000004 -- ! bicb 000003,000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000000 -- ! bicb 000003,000006 -> n0z0v0c0; 000004
d=000004 -- !
d=000000 -- ! bicb 000003,000014 -> n0z0v0c0; 000014
d=000014 -- !
d=000000 -- ! bicb 000300,000140 -> n0z0v0c0; 000040
d=000040 -- !
d=000004 -- ! bicb 000300,000300 -> n0z1v0c0; 000000
d=000000 -- !
#--------
C Exec test 46.15brc0: BISB - reg, C=0
#
wal 013246 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
150405 -- iut= bisb r4,r5
wr0 177776 -- r0=177776
wr1 000006 -- r1=6
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
cres
stapc 013240 -- start @ 13240 (2op reg)
wtgo
rpc d=013262 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 12
d=000004 -- ! bisb 000000,000000 -> n0z1v0c0; 000000
d=000000 -- !
d=000000 -- ! bisb 000003,000000 -> n0z0v0c0; 000003
d=000003 -- !
d=000000 -- ! bisb 000003,000006 -> n0z0v0c0; 000007
d=000007 -- !
d=000000 -- ! bisb 000003,000014 -> n0z0v0c0; 000017
d=000017 -- !
d=000010 -- ! bisb 000300,000140 -> n1z0v0c0; 000340
d=000340 -- !
d=000010 -- ! bisb 000300,000300 -> n1z0v0c0; 000300
d=000300 -- !
#--------
C Exec test 46.15brc1: BISB - reg, C=1
#
wal 013246 -- setup test instructions:
bwm 2
000261 -- ccmov= sec
150405 -- iut= bisb r4,r5
wr0 177776 -- r0=177776
wr1 000006 -- r1=6
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
cres
stapc 013240 -- start @ 13240 (2op reg)
wtgo
rpc d=013262 -- ! pc=halt
rr1 d=000000 -- ! r1=0
wal 037000 -- check result area
brm 12
d=000005 -- ! bisb 000000,000000 -> n0z1v0c1; 000000
d=000000 -- !
d=000001 -- ! bisb 000003,000000 -> n0z0v0c1; 000003
d=000003 -- !
d=000001 -- ! bisb 000003,000006 -> n0z0v0c1; 000007
d=000007 -- !
d=000001 -- ! bisb 000003,000014 -> n0z0v0c1; 000017
d=000017 -- !
d=000011 -- ! bisb 000300,000140 -> n1z0v0c1; 000340
d=000340 -- !
d=000011 -- ! bisb 000300,000300 -> n1z0v0c1; 000300
d=000300 -- !
#--------
C Exec test 46.17br: CMPB - reg
#
wal 036000 -- setup test vector: for cmp (b)
bwm 38
000000 -- cmpb 000000,000000
000000 --
000001 -- cmpb 000001,000000
000000 --
000377 -- cmpb 000377,000000
000000 --
000000 -- cmpb 000000,000001
000001 --
000001 -- cmpb 000001,000001
000001 --
000377 -- cmpb 000377,000001
000001 --
000176 -- cmpb 000176,000177
000177 --
000177 -- cmpb 000177,000177
000177 --
000200 -- cmpb 000200,000177
000177 --
000001 -- cmpb 000001,000177
000177 --
000377 -- cmpb 000377,000177
000177 --
000177 -- cmpb 000177,000200
000200 --
000200 -- cmpb 000200,000200
000200 --
000201 -- cmpb 000201,000200
000200 --
000001 -- cmpb 000001,000200
000200 --
000377 -- cmpb 000377,000200
000200 --
000000 -- cmpb 000000,000377
000377 --
000001 -- cmpb 000001,000377
000377 --
000377 -- cmpb 000377,000377
000377 --
wal 013246 -- setup test instructions:
bwm 2
000241 -- ccmov= clc
120405 -- iut= cmpb r4,r5
wr0 177776 -- r0=177776
wr1 000023 -- r1=23 (19.)
wr2 036000 -- r2=36000
wr3 037000 -- r3=37000
wr4 000000 -- r4=0
wr5 000000 -- r5=0
wsp 001400 -- sp=1400
cres
stapc 013240 -- start @ 13240 (2op reg)
wtgo
rpc d=013262 -- ! pc=halt
rr1 d=000000 -- ! r1=0 (Note: C=1 if dst > src unsigned)
wal 037000 -- check result area (Note: V=1 if s xor d and r eq d)
brm 38
d=000004 -- ! cmpb 000000,000000 -> n0z1v0c0; (000000)
d=000000 -- !
d=000000 -- ! cmpb 000001,000000 -> n0z0v0c0; (000001)
d=000000 -- !
d=000010 -- ! cmpb 000377,000000 -> n1z0v0c0; (000377)
d=000000 -- !
d=000011 -- ! cmpb 000000,000001 -> n1z0v0c1; (000377+C)
d=000001 -- !
d=000004 -- ! cmpb 000001,000001 -> n0z1v0c0; (000000)
d=000001 -- !
d=000010 -- ! cmpb 000377,000001 -> n1z0v0c0; (000376)
d=000001 -- !
d=000011 -- ! cmpb 000176,000177 -> n1z0v0c1; (000377+C)
d=000177 -- !
d=000004 -- ! cmpb 000177,000177 -> n0z1v0c0; (000000)
d=000177 -- !
d=000002 -- ! cmpb 000200,000177 -> n0z0v1c0; (000001)
d=000177 -- !
d=000011 -- ! cmpb 000001,000177 -> n1z0v0c1; (000202+C)
d=000177 -- !
d=000010 -- ! cmpb 000377,000177 -> n1z0v0c0; (000200)
d=000177 -- !
d=000013 -- ! cmpb 000177,000200 -> n1z0v1c1; (000377+C)
d=000200 -- !
d=000004 -- ! cmpb 000200,000200 -> n0z1v0c0; (000000)
d=000200 -- !
d=000000 -- ! cmpb 000201,000200 -> n0z0v0c0; (000001)
d=000200 -- !
d=000013 -- ! cmpb 000001,000200 -> n1z0v1c1; (000201+C)
d=000200 -- !
d=000000 -- ! cmpb 000377,000200 -> n0z0v0c0; (000177)
d=000200 -- !
d=000001 -- ! cmpb 000000,000377 -> n0z0v0c1; (000001+C)
d=000377 -- !
d=000001 -- ! cmpb 000001,000377 -> n0z0v0c1; (000002+C)
d=000377 -- !
d=000004 -- ! cmpb 000377,000377 -> n0z1v0c0; (000000)
d=000377 -- !
#-----------------------------------------------------------------------------
C Setup code 47 [base 13400] (pipeline torture tests)
#
wal 013400 -- data:
wmi 000077 -- marker
wal 013402 -- code 1:
bwm 13
016727 -- mov -6(pc),(pc)+ ;
177772
000000 -- halt ; will be overwritten
016737 -- mov -10(pc),@(pc)+ ;
177770
013400
005200 -- inc r0 ;
#13420
010317 -- mov r3,(pc) ; will overwrite next instruction
000000 -- halt ; will be overwritten
005200 -- inc r0 ;
010447 -- mov r4,-(pc) ; will overwrite itself
005200 -- inc r0 ;
000000 -- halt ;
#
wal 013440 -- code 2: (pipeline tester adapted from KDJ11A.MAC)
bwm 15
012717 -- mov (pc)+,(pc) ; will replace jmp (r1) with nop
000240 -- nop
000111 -- jmp (r1)
012717 -- mov (pc)+,(pc) ; will replace jmp (r1) with nop
000240 -- nop
000111 -- jmp (r1)
012717 -- mov (pc)+,(pc) ; will replace jmp (r1) with nop
000240 -- nop
#13460
000111 -- jmp (r1)
012717 -- mov (pc)+,(pc) ; will replace jmp (r1) with nop
000240 -- nop
000111 -- jmp (r1)
000000 -- halt ; should halt here !
000000 -- halt ;
000000 -- halt ; should not jmp here !
#
C Exec code 47 (pipeline torture tests)
C Exec test 47.1 (some self-modifying code, use (pc)+, (pc), -(pc)):
#
wr0 000000 -- r0=0
wr1 000000 -- r1=0
wr2 000000 -- r2=0
wr3 005201 -- r3= inc r1
wr4 005202 -- r4= inc r2
cres
stapc 013402 -- start @ 13402
wtgo
rpc d=013434 -- ! pc
rr0 d=000003 -- ! r0
rr1 d=000001 -- ! r1
rr2 d=000001 -- ! r2
rr3 d=005201 -- ! r3
rr4 d=005202 -- ! r4
#
wal 013400 -- check data area:
rmi d=177772 -- ! new marker ; written by mov -10(pc),@(pc)+
wal 013402 -- check code area:
brm 13
d=016727 -- ! mov -6(pc),(pc)+ ;
d=177772 -- !
d=000077 -- ! ; written by mov -6(pc),(pc)+
d=016737 -- ! mov -10(pc),@(pc)+;
d=177770 -- !
d=013400 -- !
d=005200 -- ! inc r0 ;
#13320
d=010317 -- ! mov r3,(pc) ;
d=005201 -- ! inc r1 ; written by mov r3,(pc); executed
d=005200 -- ! inc r0 ;
d=005202 -- ! inc r2 ; written by mov r4,-(pc); executed
d=005200 -- ! inc r0 ;
d=000000 -- ! halt ;
#
C Exec test 47.1 (pipeline tester adapted from KDJ11A.MAC, test 121, p. 70)
#
wr1 013474 -- r1=13474 (alternate halt)
cres
stapc 013440 -- start @ 13440
wtgo
rpc d=013472 -- ! pc
wal 013440 -- check code area:
brm 13
d=012717 -- ! mov (pc)+,(pc) ;
d=000240 -- ! nop
d=000240 -- ! nop ; written; executed
d=012717 -- ! mov (pc)+,(pc) ;
d=000240 -- ! nop
d=000240 -- ! nop ; written; executed
d=012717 -- ! mov (pc)+,(pc) ;
d=000240 -- ! nop
#13360
d=000240 -- ! nop ; written; executed
d=012717 -- ! mov (pc)+,(pc) ;
d=000240 -- ! nop
d=000240 -- ! nop ; written; executed
d=000000 -- ! halt ;
#-----------------------------------------------------------------------------
C Setup code 50 [base 13500] (check that all reserved instructions trap to 10)
#
wal 013500 -- code (to be single stepped...)
bwm 17
000007 -- 000007
000010 -- 000010-000077
000077 --
000210 -- 000210-000227
000227 --
007000 -- 007000-007777
007777 --
075000 -- 075000-076777
#13420
076777 --
106400 -- 106400-106477
106477 --
106700 -- 106700-106777
106777 --
107000 -- 107000-107777
107777 --
170000 -- 170000-177777 (no FPU)
#13440
177777 --
#
C Exec code 50 (check that all reserved instructions trap to 10)
C Test odd address abort
#
cres -- console reset
wps 000000 -- clear psw
wal 001374 -- clean stack
bwm 2
000000 --
000000 --
wsp 001400 -- sp=1400
wpc 013500 -- pc=13500
step -- step (000007): trap 10 [[s:2]]
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]]
rsp d=001374 -- ! sp=1374
#
wsp 001400 -- sp=1400
wpc 013502 -- pc=13502
step -- step (000010): trap 10 [[s:2]]
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]]
rsp d=001374 -- ! sp=1374
#
wsp 001400 -- sp=1400
wpc 013504 -- pc=13504
step -- step (000077): trap 10 [[s:2]]
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]]
rsp d=001374 -- ! sp=1374
#
wsp 001400 -- sp=1400
wpc 013506 -- pc=13506
step -- step (000210): trap 10 [[s:2]]
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]]
rsp d=001374 -- ! sp=1374
#
wsp 001400 -- sp=1400
wpc 013510 -- pc=13510
step -- step (000227): trap 10 [[s:2]]
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]]
rsp d=001374 -- ! sp=1374
#
wsp 001400 -- sp=1400
wpc 013512 -- pc=13512
step -- step (007000): trap 10 [[s:2]]
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]]
rsp d=001374 -- ! sp=1374
#
wsp 001400 -- sp=1400
wpc 013514 -- pc=13514
step -- step (007777): trap 10 [[s:2]]
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]]
rsp d=001374 -- ! sp=1374
#
wsp 001400 -- sp=1400
wpc 013516 -- pc=13516
step -- step (075000): trap 10 [[s:2]]
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]]
rsp d=001374 -- ! sp=1374
#
wsp 001400 -- sp=1400
wpc 013520 -- pc=13520
step -- step (076777): trap 10 [[s:2]]
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]]
rsp d=001374 -- ! sp=1374
#
wsp 001400 -- sp=1400
wpc 013522 -- pc=13522
step -- step (106400): trap 10 [[s:2]]
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]]
rsp d=001374 -- ! sp=1374
#
wsp 001400 -- sp=1400
wpc 013524 -- pc=13524
step -- step (106477): trap 10 [[s:2]]
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]]
rsp d=001374 -- ! sp=1374
#
wsp 001400 -- sp=1400
wpc 013526 -- pc=13526
step -- step (106700): trap 10 [[s:2]]
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]]
rsp d=001374 -- ! sp=1374
#
wsp 001400 -- sp=1400
wpc 013530 -- pc=13530
step -- step (106777): trap 10 [[s:2]]
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]]
rsp d=001374 -- ! sp=1374
#
wsp 001400 -- sp=1400
wpc 013532 -- pc=13532
step -- step (107000): trap 10 [[s:2]]
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]]
rsp d=001374 -- ! sp=1374
#
wsp 001400 -- sp=1400
wpc 013534 -- pc=13534
step -- step (107777): trap 10 [[s:2]]
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]]
rsp d=001374 -- ! sp=1374
#
wsp 001400 -- sp=1400
wpc 013536 -- pc=13536
step -- step (170000): trap 10 [[s:2]]
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]]
rsp d=001374 -- ! sp=1374
#
wsp 001400 -- sp=1400
wpc 013540 -- pc=13540
step -- step (177777): trap 10 [[s:2]]
rpc d=000012 -- ! pc=12 (trap 12 catch) [[s:14]]
rsp d=001374 -- ! sp=1374
#-----------------------------------------------------------------------------
#
C Verify trap catchers integrity
#
wal 000004 -- vectors: 4...34 (trap catcher)
brm 14
d=000006 -- ! PC:06 ; vector 4
d=000000 -- ! PS:0
d=000012 -- ! PC:12 ; vector 10
d=000000 -- ! PS:0
d=000016 -- ! PC:16 ; vector 14 (T bit; BPT)
d=000000 -- ! PS:0
d=000022 -- ! PC:22 ; vector 20 (IOT)
d=000000 -- ! PS:0
d=000026 -- ! PC:26 ; vector 24 (Power fail, not used)
d=000000 -- ! PS:0
d=000032 -- ! PC:32 ; vector 30 (EMT)
d=000000 -- ! PS:0
d=000036 -- ! PC:36 ; vector 34 (TRAP)
d=000000 -- ! PS:0
wal 000240 -- vectors: 240,244,250 (trap catcher)
brm 6
d=000242 -- ! PC:242 ; vector 240 (PIRQ)
d=000000 -- ! PS:0
d=000246 -- ! PC:246 ; vector 244 (FPU)
d=000000 -- ! PS:0
d=000252 -- ! PC:252 ; vector 250 (MMU)
d=000000 -- ! PS:0
#
C Verify setup MMU
# to avoid seeing AIB bits:
# 1. check ARs; 2. re-write ARs to clear AIBs in DRs; 3. check DRs
#
wal 172340 -- kernel I space AR
brm 8
d=000000 -- ! 0
d=000200 -- ! 200 020000 base
d=000400 -- ! 400 040000 base
d=000600 -- ! 600 060000 base
d=001000 -- ! 1000 100000 base
d=001200 -- ! 1200 120000 base
d=001400 -- ! 1400 140000 base
d=177600 -- !176000 (map to I/O page)
#
wal 172340 -- kernel I space AR
bwm 8
000000 -- 0
000200 -- 200 020000 base
000400 -- 400 040000 base
000600 -- 600 060000 base
001000 -- 1000 100000 base
001200 -- 1200 120000 base
001400 -- 1400 140000 base
177600 -- 176000 (map to I/O page)
#
wal 172300 -- kernel I space DR
brm 8
d=077406 -- ! slf=127; ed=0(up); acf=6(w/r)
d=077406 -- ! slf=127; ed=0(up); acf=6(w/r)
d=077406 -- ! slf=127; ed=0(up); acf=6(w/r)
d=077406 -- ! slf=127; ed=0(up); acf=6(w/r)
d=077406 -- ! slf=127; ed=0(up); acf=6(w/r)
d=077406 -- ! slf=127; ed=0(up); acf=6(w/r)
d=077406 -- ! slf=127; ed=0(up); acf=6(w/r)
d=077406 -- ! slf=127; ed=0(up); acf=6(w/r)
#
wal 000000 -- last cmd shouldn't be 21 or 23 ...