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[/] [w11/] [tags/] [w11a_V0.74/] [rtl/] [w11a/] [tb/] [tb_pdp11core_ubmap.dat] - Rev 40
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# $Id: tb_pdp11core_ubmap.dat 674 2015-05-04 16:17:40Z mueller $## Revision History:# Date Rev Version Comment# 2015-05-03 674 1.5 start/stop/suspend overhaul# 2008-03-02 121 1.0 extracted from sys/tb/tb_s3board_pdp11core_mem70#.mode pdpcp.tocmd 50.tostp 100.togo 5000.rlmon 0.rbmon 0#.reset.wait 10.anena 1##-----------------------------------------------------------------------------C Test 1: Write/Read ubmap registerswal 170200bwm 64177777 -- write all bits177777 -- write all bits000100 -- map 1000001000200 -- map 2000002000300 -- map 3000003000400 -- map 4000004000500 -- map 5000005000600 -- map 6000006000700 -- map 7000007001000 -- map 10000010001100 -- map 11000011001200 -- map 12000012001300 -- map 13000013001400 -- map 14000014001500 -- map 15000015001600 -- map 16000016001700 -- map 17000017002000 -- map 20000020002100 -- map 21000021002200 -- map 22000022002300 -- map 23000023002400 -- map 24000024002500 -- map 25000025002600 -- map 26000026002700 -- map 27000027003000 -- map 30000030003100 -- map 31000031003200 -- map 32000032003300 -- map 33000033003400 -- map 34000034003500 -- map 35000035003600 -- map 36000036003700 -- map 37000037wal 170200brm 64d=177776 -- only 15:01 are writable, bit 0 is 0d=000077 -- only 5:00 are writable, upper 10 bits are 0d=000100 -- map 1d=000001d=000200 -- map 2d=000002d=000300 -- map 3d=000003d=000400 -- map 4d=000004d=000500 -- map 5d=000005d=000600 -- map 6d=000006d=000700 -- map 7d=000007d=001000 -- map 10d=000010d=001100 -- map 11d=000011d=001200 -- map 12d=000012d=001300 -- map 13d=000013d=001400 -- map 14d=000014d=001500 -- map 15d=000015d=001600 -- map 16d=000016d=001700 -- map 17d=000017d=002000 -- map 20d=000020d=002100 -- map 21d=000021d=002200 -- map 22d=000022d=002300 -- map 23d=000023d=002400 -- map 24d=000024d=002500 -- map 25d=000025d=002600 -- map 26d=000026d=002700 -- map 27d=000027d=003000 -- map 30d=000030d=003100 -- map 31d=000031d=003200 -- map 32d=000032d=003300 -- map 33d=000033d=003400 -- map 34d=000034d=003500 -- map 35d=000035d=003600 -- map 36d=000036d=003700 -- map 37d=000037##-----------------------------------------------------------------------------C Test 2: Write/Read memory via bwm/brm and Unibus map#wal 170200 -- setup test mapbwm 4000000 -- map 0: 000000 -> 000000000000 --004000 -- map 1: 020000 -> 004000000000wal 170200 -- verify test mapbrm 4d=000000 -- map 0d=000000 --d=004000 -- map 1d=000000#C Test 2.1 write/read with ubmap off in MMU#wal 020000 -- Page 1wah 000200 -- ubmap=1bwm 4000100000101000102000103wal 020000brm 4d=000100d=000101d=000102d=000103#C Test 2.2 write/read with ubmap on in MMU#wal 172516 -- SSR3wm 000040 -- set ubmap=1wal 020000 -- Page 1wah 000200 -- ubmap=1bwm 4000200000201000202000203wal 020000 -- check that old transfer data unchangedbrm 4d=000100d=000101d=000102d=000103wal 004000 -- 020000 was mapped to 004000, check databrm 4d=000200d=000201d=000202d=000203#-----------------------------------------------------------------------------C Test 3: Write/Read memory via bwm/brm and Unibus map while CPU runningC Setup trap catchers## FU DATA Cwal 000004 -- vectors: 4...34 (trap catcher)bwm 14000006 -- PC:06 ; vector 4000000 -- PS:0000012 -- PC:12 ; vector 10000000 -- PS:0000016 -- PC:16 ; vector 14 (T bit; BPT)000000 -- PS:0000022 -- PC:22 ; vector 20 (IOT)000000 -- PS:0000026 -- PC:26 ; vector 24 (Power fail, not used)000000 -- PS:0000032 -- PC:32 ; vector 30 (EMT)000000 -- PS:0000036 -- PC:36 ; vector 34 (TRAP)000000 -- PS:0wal 000240 -- vectors: 240,244,250 (trap catcher)bwm 6000242 -- PC:242 ; vector 240 (PIRQ)000000 -- PS:0000246 -- PC:246 ; vector 244 (FPU)000000 -- PS:0000252 -- PC:252 ; vector 250 (MMU)000000 -- PS:0#C Setup Code#wal 002000bwm 7005211 -- inc (r1) ; increment a mem location005312 -- dec (r2) ; decrement a ubus location005700 -- tst r0 ; test for loop001774 -- beq .-4 ; loop while r0=0011103 -- mov (r1),r3 ; sum mem and ubus location061203 -- add (r2),r3 ; r3 should be 0000000 -- halt#C Start Codewr0 000000 -- 0 for loopingwr1 002100 -- a mem addrwr2 172256 -- a ubus addr: MMU SM mode AR page 7 (is a 16bit r/w reg)wpc 002000sta -- 'start' does no reset (keeps SSR3.ubmap=1)#wal 020200 -- Page 1wah 000200 -- ubmap=1bwm 16000300000301000302000303000304000305000306000307000310000311000312000313000314000315000316000317#wr0 000001 -- 1 for stop loopingwtgo -- wait for cpu halt#rpc d=002016 -- ! pcwal 002100 -- check mem loc (for visual inspection)rm d=-wal 172256 -- check ubus loc (for visual inspection)rm d=-rr3 d=000000 -- ! r3 (is sum of mem and ubus location)#wal 004200 -- 020200 was mapped to 004200, check databrm 16d=000300d=000301d=000302d=000303d=000304d=000305d=000306d=000307d=000310d=000311d=000312d=000313d=000314d=000315d=000316d=000317
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