URL
https://opencores.org/ocsvn/wb_builder/wb_builder/trunk
Subversion Repositories wb_builder
[/] [wb_builder/] [trunk/] [rtl/] [vhdl/] [wishbone.defines] - Rev 2
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# Generated by PERL program wishbone.pl.
# File used as input for wishbone arbiter generation
# Generated Fri Apr 30 16:20:22 2004
filename=wb
intercon=intercon
syscon=syscon
target=altera
hdl=vhdl
signal_groups=1
tga_bits=2
tgc_bits=3
tgd_bits=0
rename_tga=bte
rename_tgc=cti
rename_tgd=tgd
classic=000
endofburst=111
dat_size=32
adr_size=32
mux_type=andor
interconnect=crossbarswitch
master or32_i
type=ro
lock_o=0
tga_o=1
tgc_o=1
tgd_o=0
err_i=1
rty_i=1
priority_uart=0
priority_bootRAM=3
end master or32_i
master or32_d
type=rw
lock_o=0
tga_o=1
tgc_o=1
tgd_o=0
err_i=1
rty_i=1
priority_uart=1
priority_bootRAM=1
end master or32_d
slave uart
type=rw
adr_i_hi=4
adr_i_lo=0
tga_i=0
tgc_i=0
tgd_i=0
lock_i=0
err_o=0
rty_o=0
baseadr=0x90000000
size=0x00100000
baseadr1=0x00000000
size1=0xffffffff
baseadr2=0x00000000
size2=0xffffffff
end slave uart
slave bootRAM
type=rw
adr_i_hi=11
adr_i_lo=2
tga_i=0
tgc_i=0
tgd_i=0
lock_i=0
err_o=0
rty_o=0
baseadr=0x00000000
size=0x00100000
baseadr1=0x00000000
size1=0xffffffff
baseadr2=0x00000000
size2=0xffffffff
end slave bootRAM
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