Subversion Repositories wb_conmax


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write_file -hierarchy -format db -output $pre_comp_db_fileecho "+++++++++ Saving Design ..."                      >> $log_file# Save Design# ==============================================check_design >> $log_fileecho "+++++++++ Checking Design ..."                    >> $log_fileuniquify >> $log_fileecho "+++++++++ Uniquifying Design ..."                 >> $log_filelink >> $log_fileecho "+++++++++ Linking Design ..."                     >> $log_filecurrent_design $active_design   }        elaborate $module                               >> $log_file        analyze -f verilog $module_file_name            >> $log_file        append module_file_name $module ".v"        set module_file_name ""        echo +++++++++ Reading: $module        echo "+++++++++ Reading: $module"               >> $log_fileforeach module $design_files {echo "+++++++++ Analyzing all design files ..."         >> $log_file# Read Design# ==============================================set hdlin_enable_vpp true       ;# Important - this enables 'ifdefs# Setup Misc Variables# ==============================================sh rm -f $log_fileappend pre_comp_db_file    ../out/$design_name "_pre.db"append log_file           ../log/$active_design "_pre.log"# Setup IO Files# ==============================================source ../bin/lib_spec.dc# Setup Libraries# ==============================================source ../bin/design_spec.dc# Setup Design Parameters# ==============================================################################################################################## 3/7/01 RU Initial Sript# Revision:##         rudi@asics.ws# Author: Rudolf Usselmann## This script only reads in the design and saves it in a DB file## Pre Synthesis Script################################################################################