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https://opencores.org/ocsvn/wb_conmax/wb_conmax/trunk
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[/] [wb_conmax/] [trunk/] [syn/] [bin/] [design_spec.dc] - Rev 6
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###############################################################################
#
# Design Specification
#
# Author: Rudolf Usselmann
# rudi@asics.ws
#
# Revision:
# 17/10/01 RU Initial Sript
#
#
###############################################################################
# ==============================================
# Setup Design Parameters
set design_files {wb_conmax_pri_dec wb_conmax_pri_enc wb_conmax_arb wb_conmax_msel wb_conmax_slave_if wb_conmax_master_if wb_conmax_rf wb_conmax_top}
set design_name wb_conmax_top
set active_design wb_conmax_top
# Next Statement defines all clocks and resets in the design
set special_net {rst_i clk_i}
set hdl_src_dir ../../rtl/verilog/