Subversion Repositories wb_dma

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#
# Design Specification
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# Author: Rudolf Usselmann
#         rudi@asics.ws
#
# Revision:
# 3/7/01 RU Initial Sript
#
#
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# ==============================================
# Setup Design Parameters

set design_files {wb_dma_inc30r wb_dma_ch_arb wb_dma_pri_enc_sub wb_dma_ch_pri_enc wb_dma_ch_sel wb_dma_ch_rf wb_dma_rf wb_dma_wb_mast wb_dma_wb_slv  wb_dma_wb_if wb_dma_de wb_dma_top }

set design_name wb_dma_top
set active_design wb_dma_top
 
# Next Statement defines all clocks and resets in the design
set special_net {rst clk}
 
set hdl_src_dir ../../rtl/verilog/