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////  $Id: README.TXT,v 1.2 2008-03-11 04:39:49 hharte Exp $      ////
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////  This file is part of the Wishbone LPC Bridge project        ////
////  http://www.opencores.org/projects/wb_lpc/                   ////
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////  Author:                                                     ////
////      - Howard M. Harte (hharte@opencores.org)                ////
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//// Copyright (C) 2008 Howard M. Harte                           ////
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//// This source file may be used and distributed without         ////
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//// This source file is free software; you can redistribute it   ////
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//// Public License as published by the Free Software Foundation; ////
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//// This source is distributed in the hope that it will be       ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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Wishbone LPC Bridge Samples:

1. pci_lpc/     PCI to LPC Host Controller using the Enterpoint Raggedstone1 FPGA card.
2. lpc_7seg/    LPC 7-Segment Display Peripheral using the Raggedstone1 FPGA card.

To use these example, you will need two Raggedstone1 boards.  The first board is the PCI to LPC host, and the second board is the LPC device.  The two Raggedstone1 cards are connected together by making a short ribbon cable using 16-pin DIP IDC connectors.  The topmost pins of JR1/JR2 is where this cable plugs in.

The LPC bus is pinned out as follows, on JR2:

W1 LPC_CLK  - Buffered version of PCI_CLK, phase shifted by about -3ns.
W2 LFRAME#  - LPC Framing indication.
V5 LAD<0>   - LPC Address/Data/Command Bus (LSB).
U5 LAD<1>   - LPC Address/Data/Command Bus.
V2 LAD<2>   - LPC Address/Data/Command Bus.
V1 LAD<3>   - LPC Address/Data/Command Bus (MSB).
U4 LPC_RST# - active-low reset, buffered version of PCI_RST#
T4 LPC_INT  - Serial IRQ, pulled up at host.

If you only have one Raggedstone1 PCI card, these designs could be combined and run on a single card.