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PK

__OBJSTORE__/PK
__OBJSTORE__/Autonym/PK
#__OBJSTORE__/ExpandedNetlistEngine/PK
 __OBJSTORE__/HierarchicalDesign/PK
*__OBJSTORE__/HierarchicalDesign/HDProject/PK
__OBJSTORE__/PnAutoRun/PK
__OBJSTORE__/PnAutoRun/Scripts/PK
namespace eval Dpm {
proc GetIseVersion {} {
   set fsetName "fileset.txt"
   set fsetPath ""
   # Find the file in the Xilinx environment.
   # First, construct the environment path.
   set sep ":"; # Default to UNIX style seperator.
   if {[string compare -length 7 $::tcl_platform(platform) "windows"] == 0} {
      set sep ";"; # Platform is a Windows variant, so use semi-colon.
   }
   set xilinxPath $::env(XILINX)
   if [info exists ::env(MYXILINX)] then {
      set xilinxPath [join [list $::env(MYXILINX) $xilinxPath] $sep]
   }
   # Now look in each path of the path until we find a match.
   foreach xilElem [split $xilinxPath $sep] {
      set checkPath ${xilElem}/$fsetName
      set checkPath [ string map { \\ / } $checkPath ]
      if { [file exists $checkPath] } {
         set fsetPath $checkPath
         break
      }
   }
   if { [string equal $fsetPath ""] } {
      puts "ERROR: Can not determine the ISE software version."
      return ""
   }
   if { [catch { open $fsetPath r } fset] } {
      puts "ERROR: Could not open $fsetPath: $fset"
      return ""
   }
   # have the file open, scan for the version entry.
   set sVersion ""
   while { ![eof $fset] } {
      set line [gets $fset]
      regexp {version=(.*)} $line match sVersion
         # The above doesn't stop looking in the file. This assumes that if
         # there are multiple version entries, the last one is the one we want.
   }
   close $fset
   return $sVersion
}
proc CheckForIron {project_name} {
   
   # Determine if the currently running version of ProjNav is earlier than Jade.
   set version [GetIseVersion]
   set dotLocation [string first "." $version]
   set versionBase [string range $version 0 [expr {$dotLocation - 1}]]
   if {$versionBase < 9} {
      
      # The project file is newer than Iron, so take action to prevent the
      # file from being corrupted.
      # Make the file read-only.
      if {[string compare -length 7 $::tcl_platform(platform) "windows"]} {
         # The above will return 0 for a match to "windows" or "windows64".
         # This is the non-zero part of the if, for lin and sol.
         # Change the permissions to turn off writability.
         file attributes $project_name -permissions a-w
      } else {
         # On Windows, set file to read-only.
         file attributes $project_name -readonly 1
      }      
      
      # And tell the user about it.
      set messageText "WARNING: This project was last saved with a newer version of Project Navigator.\nThe project file will be made read-only so that it will not be invalidated by this version."
      # In the console window
      puts $messageText
      # And with a GUI message box if possible.
      ::xilinx::Dpm::TOE::loadGuiLibraries
      set iInterface 0
      set messageDisplay 0
      if {[catch {
         set iInterface [Xilinx::CitP::GetInstance $::xilinx::GuiI::IMessageDlgID]
         set messageDisplay [$iInterface GetInterface $::xilinx::GuiI::IMessageDlgID]
         if {$messageDisplay != 0} {
            # Managed to get a component to display a dialog, so use it
            set messageTitle "Incompatible Project Version (Newer)"
            set messageType 2
               # 2 corresponds to a warning dialog. TclWrapGuiI_Init.cpp doesn't put the enum into Tcl.
            set messageTimeout 300000
               # in milliseconds, 5 minutes
            set messageReturn [$messageDisplay MessageDlg $messageTitle $messageText $messageType 1 1 $messageTimeout "OK" "" ""]
         }
      } catchResult]} {
         # There was an error, probably because we aren't in a GUI enviroment.
      } else {
         # All is well.
      }
      set messageDisplay 0
      set iInterface 0
   }
      
   return 1
}
}
}
::xilinx::Dpm::CheckForIronPK
__OBJSTORE__/ProjectNavigator/PK
/__OBJSTORE__/ProjectNavigator/dpm_project_main/PK
H[''F__OBJSTORE__/ProjectNavigator/dpm_project_main/dpm_project_main_StrTbllpc_7segspartan3espartan3PK
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IN_General|1216948046|FILE_MFP|Generic||lpc_7seg.mfplpc_7seg.mfpDESUT_MFP|File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/_xmsgs/bitgen.xmsgs|PLUGIN_General|1216953915|FILE_XMSGS|Generic||bitgen.xmsgsbitgen.xmsgsDESUT_XMSGS|File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/lpc_7seg.bgn|PLUGIN_General|1216953915|FILE_BITGEN_REPORT|Generic||lpc_7seg.bgnlpc_7seg.bgnDESUT_BITGEN_REPORT|File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/lpc_7seg.bit|PLUGIN_General|1216953914|FILE_BIT|Generic||lpc_7seg.bitlpc_7seg.bitDESUT_BIT|File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/lpc_7seg.drc|PLUGIN_General|1216953912|FILE_BITGEN_DRC|Generic||lpc_7seg.drclpc_7seg.drcDESUT_BITGEN_DRC|File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/_xmsgs/trce.xmsgs|PLUGIN_General|1216953909||Generic||trce.xmsgstrce.xmsgs|File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/lpc_7seg.twx|PLUGIN_General|1216953909|FILE_TIMING_XML_REPORT|Generic||lpc_7seg.twxlpc_7seg.twxDESUT_TIMING_XML_REPORT|File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/lpc_7seg.twr|PLUGIN_General|1216953909|FILE_TIMING_TXT_REPORT|Generic||lpc_7seg.twrlpc_7seg.twrDESUT_TIMING_TXT_REPORT|File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/_xmsgs/par.xmsgs|PLUGIN_General|1216953906||Generic||par.xmsgspar.xmsgs|File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/lpc_7seg_pad.csv|PLUGIN_General|1216953906|FILE_PAD_EXCEL_REPORT|Generic||lpc_7seg_pad.csvlpc_7seg_pad.csvDESUT_PAD_EXCEL_REPORT|File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/lpc_7seg_pad.txt|PLUGIN_General|1216953906|FILE_PAD_TXT_REPORT|Generic||lpc_7seg_pad.txtlpc_7seg_pad.txtDESUT_PAD_TXT_REPORTTBIND_viewPadRptsTRAN_viewPadRpts|File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/lpc_7seg_par.xrpt|PLUGIN_General|1216953906|FILE_XRPT|Generic||lpc_7seg_par.xrptlpc_7seg_par.xrptDESUT_GENERIC|File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/lpc_7seg.xpi|PLUGIN_General|1216953906|FILE_XPI|Generic||lpc_7seg.xpilpc_7seg.xpiDESUT_XPI|File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/lpc_7seg.unroutes|PLUGIN_General|1216953906|FILE_UNROUTES|Generic||lpc_7seg.unrouteslpc_7seg.unroutesDESUT_UNROUTES|File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/lpc_7seg.par|PLUGIN_General|1216953906|FILE_PAR_REPORT|Generic||lpc_7seg.parlpc_7seg.parDESUT_PAR_REPORTTBIND_viewParRptsTRAN_viewParRpts|File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/lpc_7seg.pad|PLUGIN_General|1216953906|FILE_PAD_MISC|Generic||lpc_7seg.padlpc_7seg.padDESUT_PAD_MISC|File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/lpc_7seg.ncd|PLUGIN_NCD|1216953906|PLUGIN_NCDFILE_NCD|Module||lpc_7segDESUT_NCD|File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/_xmsgs/map.xmsgs|PLUGIN_General|1216953895||Generic||map.xmsgsmap.xmsgs|File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/lpc_7seg_usage.xml|PLUGIN_General|1216953895|FILE_WEBTALK|Generic||lpc_7seg_usage.xmllpc_7seg_usage.xml|File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/lpc_7seg_map.ngm|PLUGIN_NGM|1216953894|PLUGIN_NGMFILE_NGMDESUT_NGM3s400fg456-4|File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/lpc_7seg.pcf|PLUGIN_General|1216953894|FILE_PCF|Generic||lpc_7seg.pcflpc_7seg.pcfDESUT_PCF|File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/lpc_7seg_map.ncd|PLUGIN_NCD|1216953895||File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/lpc_7seg_map.xrpt|PLUGIN_General|1216953895||Generic||lpc_7seg_map.xrptlpc_7seg_map.xrpt|File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/lpc_7seg_map.mrp|PLUGIN_General|1216953895|FILE_MAP_REPORT|Generic||lpc_7seg_map.mrplpc_7seg_map.mrpDESUT_MAP_REPORT|File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/_xmsgs/ngdbuild.xmsgs|PLUGIN_General|1216953891||Generic||ngdbuild.xmsgsngdbuild.xmsgs|File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/_ngo|PLUGIN_General|1216953889|FILE_DIRECTORY|Generic||_ngo_ngoDESUT_DIRECTORY|File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/_ngo/netlist.lst|PLUGIN_General|1216953891|FILE_LST|Generic||netlist.lstnetlist.lstDESUT_LST|File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/lpc_7seg.bld|PLUGIN_General|1216953891|FILE_NGDBUILD_LOG|Generic||lpc_7seg.bldlpc_7seg.bldDESUT_NGDBUILD_LOG|File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/lpc_7seg.ngd|PLUGIN_NGD|1216953890|PLUGIN_NGDFILE_NGDDESUT_NGD|File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/lpc_7seg_xdb/cst.xbcd|PLUGIN_General|1216951952|FILE_BCD|Generic||cst.xbcdcst.xbcdDESUT_BCD|File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/_xmsgs/xst.xmsgs|PLUGIN_General|1216953886||Generic||xst.xmsgsxst.xmsgs|File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/lpc_7seg.cmd_log|PLUGIN_General|1216953875|FILE_CMD_LOG|Generic||lpc_7seg.cmd_loglpc_7seg.cmd_logDESUT_CMD_LOG|File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/xst|PLUGIN_General|1216686883||Generic||xstxst|File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/lpc_7seg.ngr|PLUGIN_NGR|1216953881|PLUGIN_NGRFILE_NGRDESUT_NGR|File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/lpc_7seg.ngc|PLUGIN_NGC|1216953886|PLUGIN_NGCFILE_NGCDESUT_NGCxc3s400-4-fg456|File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/lpc_7seg_vhdl.prj|PLUGIN_General|1216953876|FILE_XST_PROJECT|Generic||lpc_7seg_vhdl.prjlpc_7seg_vhdl.prjDESUT_XST_PROJECT|File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/lpc_7seg.prj|PLUGIN_General|1216953875||Generic||lpc_7seg.prjlpc_7seg.prj|File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/lpc_7seg.syr|PLUGIN_General|1216953886|FILE_XST_REPORT|Generic||lpc_7seg.syrlpc_7seg.syrDESUT_XST_REPORT|File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/lpc_7seg.lso|PLUGIN_General|1204699959|FILE_LSO|Generic||lpc_7seg.lsolpc_7seg.lsoDESUT_LSO|File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/lpc_7seg.xst|PLUGIN_General|1216953875|FILE_XST|Generic||lpc_7seg.xstlpc_7seg.xstDESUT_XST|File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/lpc_7seg_guide.ncd|PLUGIN_NCD|1216953906||File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/wb_7seg.vhd|PLUGIN_Vhdl|1216953750|FILE_VHDL|Architecture||wb_7seg_behav|wb_7seg|||ComponentInstantiation||wb_7seg|wb_7seg_behav|u1|disp_dec||Entity||wb_7seg|Library||||Use||IEEE|STD_LOGIC_1164|all||Use||IEEE|STD_LOGIC_ARITH|all||Use||IEEE|STD_LOGIC_UNSIGNED|all|wb_7seg_behavwb_7segDESUT_VHDL_ARCHITECTUREu1disp_decDESUT_VHDL_ENTITYIEEE.STD_LOGIC_UNSIGNED.allIEEESTD_LOGIC_UNSIGNEDallIEEE.STD_LOGIC_ARITH.allSTD_LOGIC_ARITHIEEE.STD_LOGIC_1164.allSTD_LOGIC_1164|File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/top_lpc_7seg.v|PLUGIN_Verilog|1216953737|FILE_VERILOG|ComponentInstantiation||lpc_7seg|lpc_7seg|lpc_periph|wb_lpc_periph||ComponentInstantiation||lpc_7seg|lpc_7seg|seven_seg0|wb_7seg|DESUT_VERILOGseven_seg0lpc_periphwb_lpc_periph|File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/lpc_7seg.ucf|PLUGIN_AssocModule|1216687080|PLUGIN_AssocModuleFILE_UCF|Module||lpc_7seg.ucflpc_7seg.ucfDESUT_UCF|File||C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/disp_dec.vhd|PLUGIN_Vhdl|1204699959||Architecture||disp_dec_behave|disp_dec|||Entity||disp_decdisp_dec_behave|File||C:/hharte/work/HarteTec/cores/wb_lpc/rtl/verilog/wb_lpc_periph.v|PLUGIN_Verilog|1216951926||Module||wb_lpc_periphAutoGeneratedViewVIEW_AssignPackagePinsTBIND_XSTAssignPackagePinsTRAN_assignPackagePinsVIEW_XSTPreSynthesisTBINDEXT_XSTPreSynthesisToStructural_spartan3TRAN_SubProjectPreToStructuralProxyModule|lpc_7segTRAN_compileBCD2trueSpeedfalsexc3s400LUTNoXST (VHDL/Verilog)YesAuto./xst<>None100Maintain500As OptimizedAllClockNetsNormalfg456HDL8-4/TRANEXT_xstsynthesize_spartan3VIEW_StructuralTBIND_StructuralToPost-SynthesisAbstractSimulationTRAN_postSynthesisSimModelVIEW_Post-SynthesisAbstractSimulationTBINDEXT_StructuralToTranslation_FPGATimestampOffTRANEXT_ngdbuild_FPGAVIEW_TranslationTBIND_xlateFloorPlannerTRAN_xlateFloorPlannerVIEW_Post-TranslateFloorPlannerTBIND_xlateAssignPackagePinsTRAN_xlateAssignPackagePinsVIEW_Post-TranslateAssignPinsTBIND_TranslationToPost-TranslateFormalityNetlistTRAN_postXlateFormalityNetlistVIEW_Post-TranslateFormalityNetlistTBIND_TranslationToPost-TranslateAbstractSimulationTRAN_postXlateSimModelVIEW_Post-TranslateAbstractSimulationTBIND_Post-TranslateAbstractToTBWPreSimulationTRAN_createPostXlateTestBenchTRAN_copyPost-TranslateAbstractToPreSimulationVIEW_TBWPost-TranslatePreSimulationTBIND_Post-TranslateAbstractToPreSimulationVIEW_Post-TranslatePreSimulationTBIND_TranslateToSmartTRAN_CopySmartXplorerResultTRAN_SmartXplorerVIEW_SmartXplorerTBIND_NGCAssignPackagePinsTRAN_ngcAssignPackagePinsVIEW_ngcAssignPackagePinsTBIND_FloorplanDesignTRAN_floorplanDesignVIEW_Post-TranslateFloorplanDesignTBIND_CreateTimingConstraintsTRAN_createTimingConstraintsVIEW_Post-TranslateTimingConstraintsTBIND_CreateAreaConstraintsTRAN_createAreaConstraintsVIEW_Post-TranslateAreaConstraintsTBINDEXT_TranslationToMap_spartan3Area4For Inputs and OutputsTRANEXT_map_spartan3VIEW_MapTBIND_preRouteTrceTRAN_preRouteTrceVIEW_Post-MapStaticTimingTBIND_mapFpgaEditorTRAN_mapFpgaEditorVIEW_Post-MapFpgaEditorTBIND_mapFloorPlannerTRAN_mapFloorPlannerVIEW_Post-MapFloorPlannerTBIND_MapToPost-MapAbstractSimulationTRAN_postMapSimModelVIEW_Post-MapAbstractSimulationTBIND_Post-MapAbstractToTBWPreSimulationTRAN_createPostMapTestBenchTRAN_copyPost-MapAbstractToPreSimulationVIEW_TBWPost-MapPreSimulationTBIND_Post-MapAbstractToPreSimulationVIEW_Post-MapPreSimulationTBINDEXT_MapToPar_spartan31Normal Place and RouteStandardTRANEXT_par_spartan3VIEW_ParTBIND_postRouteTrce3Error ReportTRAN_postRouteTrceVIEW_Post-ParStaticTimingTBIND_postParPrimetimeNetlistTRAN_postParPrimetimeNetlistVIEW_PrimetimeNetlistTBIND_parFpgaEditorTRAN_parFpgaEditorVIEW_Post-ParFpgaEditorTBIND_parFloorPlannerTRAN_parFloorPlannerVIEW_Post-ParFloorPlannerTBIND_genPowerDataTRAN_genPowerDataVIEW_FPGAGeneratePowerDataTBIND_createIBISModelTRAN_createIBISModelVIEW_IBISModelTBIND_XpowerTRAN_XPowerVIEW_FPGAAnalyzePowerTBIND_ParToPost-ParFormalityNetlistTRAN_postParFormalityNetlistVIEW_Post-ParFormalityNetlistTBIND_ParToPost-ParClockRegionTRAN_clkRegionRptVIEW_Post-ParClockRegionReportTBIND_ParToPost-ParAsyncDelayTRAN_asynDlyRptVIEW_Post-ParAsyncDelayReportTBIND_ParToPost-ParAbstractSimulationTRAN_postParSimModelVIEW_Post-ParAbstractSimulationTBIND_Post-ParAbstractToTBWPreSimulationTRAN_createPostParTestBenchTRAN_copyPost-ParAbstractToPreSimulationVIEW_TBWPost-ParPreSimulationTBIND_TBWPost-ParPreToFuseTRAN_ISimulatePostPlace&RouteModelRunFuse(bencher)VIEW_TBWPost-ParFuseTBIND_TBWPost-ParFuseToSimulationISimTRAN_ISimulatePostPlace&RouteModel(bencher)VIEW_TBWPost-ParSimulationISimTBIND_Post-ParAbstractToPreSimulationVIEW_Post-ParPreSimulationTBIND_Post-ParPreToFuseTRAN_ISimulatePostPlace&RouteModelRunFuseVIEW_Post-ParFuseTBIND_Post-ParFuseToSimulationISimTRAN_ISimulatePostPlace&RouteModelVIEW_Post-ParSimulationISimTBIND_ParToMpprResultTRAN_copyMpprRsltVIEW_MpprResultTBIND_ParToLockedPinConstraintsTRAN_genLockedPinConstraintsVIEW_LockedPinConstraintsTBIND_ParToBackAnnoPinLocationsTRAN_backAnnoPinLocationsVIEW_BackAnnoPinLocationsTBINDEXT_ParToFPGAConfiguration_spartan3Pull UpDefault (6)Default (4)As RequiredEnable Readback and ReconfigurationCCLKPull DownDefault (NoWait)0xFFFFFFFFDefault (5)TRANEXT_bitFile_spartan3VIEW_FPGAConfigurationTBIND_analyzeDesignUsingChipscopeTRAN_analyzeDesignUsingChipscopeVIEW_AnalyzedDesignTBIND_UpdateBitstreamXPSTRAN_xpsUpdBitstreamVIEW_UpdatedBitstreamTBIND_FPGAConfigurationToFPGAGeneratePROMTRAN_genImpactFileVIEW_FPGAGeneratePROMTBIND_FPGAConfigurationToFPGAConfigureTargetDeviceTRAN_configureTargetDeviceVIEW_FPGAConfigureTargetDeviceTBIND_FPGAConfigurationToFPGAConfigureDeviceTRAN_impactProgrammingToolVIEW_FPGAConfigureDeviceTBIND_XSTAbstractToPreSynthesisTRAN_SubProjectAbstractToPreProxyTRAN_convertToHdlTRAN_copyAbstractToPreSynthesisForSynthesisVIEW_XSTAbstractSynthesis/lpc_7segTBIND_InitialToXSTAbstractSynthesisTRAN_copyInitialToXSTAbstractSynthesisVIEW_InitialTBIND_InitialToAbstractSimulationTRAN_copyInitialToAbstractSimulationVIEW_AbstractSimulationTBIND_AbstractToPostAbstractSimulationTRAN_copyAbstractToPostAbstractSimulationVIEW_PostAbstractSimulationTBIND_PostAbstractToTBWPreSimulationTRAN_viewBehavioralTestbenchTRAN_copyPostAbstractToPreSimulationVIEW_TBWPreSimulationTBIND_TBWPreToBehavioralFuseTRAN_ISimulateBehavioralModelRunFuse(bencher)VIEW_TBWBehavioralFuseTBIND_TBWBehavioralFuseToSimulationISimTRAN_ISimulateBehavioralModel(bencher)VIEW_TBWBehavioralSimulationISimTBIND_PostAbstractToPreSimulationVIEW_PreSimulationTBIND_PreToBehavioralFuseTRAN_ISimulateBehavioralModelRunFuseVIEW_BehavioralFuseTBIND_BehavioralFuseToSimulationISimTRAN_ISimulateBehavioralModelVIEW_BehavioralSimulationISimTBIND_PostAbstractToAnnotatedPreSimulationTRAN_viewBehavioralTestbenchForAnnoTRAN_copyPostAbstractToAnnotatedPreSimulationVIEW_AnnotatedPreSimulationTBIND_PreToGenerateAnnotatedResultsFuseTRAN_ISimGenerateAnnotatedResultsRunFuseTRAN_copyPreToGenerateAnnotatedResultsFuseForTBWVIEW_AnnotatedResultsFuseTBIND_FuseToAnnotatedResultsISimTRAN_ISimGenerateAnnotatedResultsTRAN_copyFuseToAnnotatedResultsISimForTBWVIEW_AnnotatedResultsISimTBIND_AnnotatedToGenerateExpectedSimulationResultsISimTRAN_ISimGenerateExpectedSimulationResultsVIEW_ExpectedSimulationResultsISimTBINDEXT_InitialToCommon_FPGATRANEXT_compLibraries_FPGAVIEW_CommonDESPF_TRADITIONALPROP_PreferredLanguageVerilogPROP_SimulatorModelsim-SE MixedISE Simulator (VHDL/Verilog)Other MixedOther VerilogOther VHDLVCS-MXi MixedVCS-MXi VerilogVCS-MXi VHDLVCS-MX MixedVCS-MX VerilogVCS-MX VHDLNC-Sim MixedNC-Sim VerilogNC-Sim VHDLModelsim-XE VerilogModelsim-XE VHDLModelsim-PE MixedModelsim-PE VerilogModelsim-PE VHDLModelsim-SE VerilogModelsim-SE VHDLPROP_Synthesis_ToolPROP_Top_Level_Module_TypeVHDLPROP_DevSpeed-5PROP_DevPackagepq208PROP_DevDevicexc3s50xc3s1500lxc3s1500xc3s1000lxc3s1000xc3s200tq144ft256fg320PROP_ParSmartGuideFileNamelpc_7seg_guide.ncdPROP_UseSmartGuidePROP_SynthTopNCD files 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 !"#$%&'()*+,-./0123456789:;<=>?@ABC*DEF*GHIJK*LMNOPQRSTUVWXYZPK
  <view program="map" inputState="Translated" type="IOBProperties" file="!module_name!_map.mrp" label="IOB Properties" />   <view program="par" inputState="Mapped" type="ConstraintsData" file="!module_name!.par" label="Timing Constraints" />   <view program="par" inputState="Mapped" type="PinoutData" file="!module_name!.pad" label="Pinout Report" />   <view program="par" inputState="Mapped" type="ClocksData" file="!module_name!.par" label="Clock Report" />  </viewgroup>  <viewgroup label="Errors and Warnings" >   <view program="xst" type="MessageList" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" hideColumns="Filtered"/>   <view program="ngdbuild" inputState="Synthesized" type="MessageList" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" hideColumns="Filtered"/>   <view program="map" inputState="Translated" type="MessageList"  file="_xmsgs/map.xmsgs" label="Map Messages" hideColumns="Filtered"/>   <view program="par" inputState="Mapped" type="MessageList"  file="_xmsgs/par.xmsgs" label="Place and Route Messages" hideColumns="Filtered"/>   <view program="trce" inputState="Routed" type="MessageList"  file="_xmsgs/trce.xmsgs" label="Timing Messages" hideColumns="Filtered"/>   <view program="bitgen" inputState="Routed" type="MessageList" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" hideColumns="Filtered"/>   <view program="implementation" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/bitgen.xmsgs" inputState="Current" type="MessageList"  file="_xmsgs/*.xmsgs" label="All Current Messages" hideColumns="Filtered"/>  <viewgroup label="Detailed Reports" >   <view program="xst" type="Report" file="!module_name!.syr" label="Synthesis Report   " >    <toc-item title="Synthesis Options Summary" target="   Synthesis Options Summary   " />    <toc-item title="HDL Compilation"           target="   HDL Compilation   " />    <toc-item title="Design Hierarchy Analysis" target="   Design Hierarchy Analysis   " />    <toc-item title="HDL Analysis"              target="   HDL Analysis   " />    <toc-item title="HDL Synthesis"             target="   HDL Synthesis   " />    <toc-item title="Advanced HDL Synthesis"    target="   Advanced HDL Synthesis   " />    <toc-item title="Low Level Synthesis"       target="   Low Level Synthesis   " />    <toc-item title="Partition Report"          target="   Partition Report     " />    <toc-item title="Final Report"              target="   Final Report   " />   <view program="ngdbuild" inputState="Synthesized" type="Report" file="!module_name!.bld" label="Translation Report" >    <toc-item title="Top of Report" target="Release" />    <toc-item title="Command Line" target="Command Line:" />    <toc-item title="Partition Status"          target="Partition Implementation Status" />    <toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />   <view program="map" inputState="Translated" type="Report" file="!module_name!_map.mrp" label="Map Report" >    <toc-item title="Section 1: Errors"                             target="Section 1 - " />    <toc-item title="Section 2: Warnings"                           target="Section 2 - " />    <toc-item title="Section 3: Infos"                              target="Section 3 - " />    <toc-item title="Section 4: Removed Logic Summary"              target="Section 4 - " />    <toc-item title="Section 5: Removed Logic"                      target="Section 5 - " />    <toc-item title="Section 6: IOB Properties"                     target="Section 6 - " />    <toc-item title="Section 7: RPMs"                               target="Section 7 - " />    <toc-item title="Section 8: Guide Report"                       target="Section 8 - " />    <toc-item title="Section 9: Area Group and Partition Summary"   target="Section 9 - " />    <toc-item title="Section 10: Modular Design Summary"            target="Section 10 - " />    <toc-item title="Section 11: Timing Report"                     target="Section 11 - " />    <toc-item title="Section 12: Configuration String Information"  target="Section 12 - " />   <view program="par" inputState="Mapped" type="Report" file="!module_name!.par" label="Place and Route Report" >    <toc-item title="Device Utilization" target="Device Utilization Summary:" />    <toc-item title="Placer Information" target="Starting Placer" />    <toc-item title="Router Information" target="Starting Router" />    <toc-item title="Partition Status"   target="Partition Implementation Status" />    <toc-item title="Clock Report"       target="Generating Clock Report" />    <toc-item title="Timing Results"     target="Timing Score:" />    <toc-item title="Final Summary"      target="Peak Memory Usage:" />   <view program="trce" inputState="Routed" type="Report" file="!module_name!.twr" label="Static Timing Report">    <toc-item title="Data Sheet Report" target="Data Sheet" />    <toc-item title="Timing Summary" target="Timing summary:" />   <view program="bitgen" inputState="Routed" type="Report" file="!module_name!.bgn" label="Bitgen Report">    <toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />    <toc-item title="Final Summary" target="DRC detected" />  <viewgroup label="Secondary Reports" >   <view program="isim" inputState="PreSynthesized" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" hidden="true"/>   <view program="map" inputState="Translated" type="Secondary_Report" file="!module_name!_map.map" label="Map Log File" hidden="true">    <toc-item title="Design Information" target="Design Information" />    <toc-item title="Design Summary"     target="Design Summary" />   <view program="xplorer" inputState="Routed" type="Secondary_Report" file="!module_name!_xplorer.rpt" label="Xplorer Report" hidden="true"/>   <view program="netgen" inputState="Translated" type="Secondary_Report" file="netgen/translate/!module_name!_translate.nlf" label="Post-Translate Simulation Model Report" hidden="true"/>   <view program="trce" inputState="Mapped" type="Secondary_Report" file="!module_name!_preroute.twr" label="Post-Map Static Timing Report"  hidden="true"/>   <view program="netgen" inputState="Mapped" type="Secondary_Report" file="netgen/map/!module_name!_map.nlf" label="Post-Map Simulation Model Report" hidden="true"/>   <view program="par" inputState="Mapped" type="Pad_Report" file="!module_name!_pad.txt" label="Pad Report"  hidden="true"/>   <view program="par" inputState="Mapped" type="Secondary_Report" file="!module_name!.unroutes" label="Unroutes Report" hidden="true"/>   <view program="par" inputState="Mapped" type="Secondary_Report" file="!module_name!.grf" label="Guide Results Report" hidden="true"/>   <view program="par" inputState="Routed" type="Secondary_Report" file="!module_name!.dly" label="Asynchronous Delay Report" hidden="true"/>   <view program="par" inputState="Routed" type="Secondary_Report" file="!module_name!.clk_rgn" label="Clock Region Report" hidden="true"/>   <view program="netgen" inputState="Routed" type="Secondary_Report" file="netgen/par/!module_name!_timesim.nlf" label="Post-Route Simulation Model Report" hidden="true"/>   <view program="xpwr" inputState="Routed" type="Report" file="!module_name!.pwr" label="Power Report"  hidden="true"/> </body></report-views>PK

 !"#$%&'()*+,-./0123456789:;<=>?-@ABC+DEF+GHIJK+LMNOPQRSTUVWXYZPK
ion Report" >   <view program="map" type="IOBProperties" inputState="Translated" file="lpc7seg_map.mrp" label="IOB Properties" />   <view program="par" type="ConstraintsData" inputState="Mapped" file="lpc7seg.par" label="Timing Constraints" />   <view program="par" type="PinoutData" inputState="Mapped" file="lpc7seg.pad" label="Pinout Report" />   <view program="par" type="ClocksData" inputState="Mapped" file="lpc7seg.par" label="Clock Report" />  </viewgroup>  <viewgroup label="Errors and Warnings" >   <view program="xst" type="MessageList" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" hideColumns="Filtered" />   <view program="ngdbuild" type="MessageList" inputState="Synthesized" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" hideColumns="Filtered" />   <view program="map" type="MessageList" inputState="Translated" file="_xmsgs/map.xmsgs" label="Map Messages" hideColumns="Filtered" />   <view program="par" type="MessageList" inputState="Mapped" file="_xmsgs/par.xmsgs" label="Place and Route Messages" hideColumns="Filtered" />   <view program="trce" type="MessageList" inputState="Routed" file="_xmsgs/trce.xmsgs" label="Timing Messages" hideColumns="Filtered" />   <view program="bitgen" type="MessageList" inputState="Routed" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" hideColumns="Filtered" />   <view fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/bitgen.xmsgs" program="implementation" type="MessageList" inputState="Current" file="_xmsgs/*.xmsgs" label="All Current Messages" hideColumns="Filtered" />  <viewgroup label="Detailed Reports" >   <view program="xst" type="Report" file="lpc7seg.syr" label="Synthesis Report   " >    <toc-item title="Synthesis Options Summary" target="   Synthesis Options Summary   " />    <toc-item title="HDL Compilation" target="   HDL Compilation   " />    <toc-item title="Design Hierarchy Analysis" target="   Design Hierarchy Analysis   " />    <toc-item title="HDL Analysis" target="   HDL Analysis   " />    <toc-item title="HDL Synthesis" target="   HDL Synthesis   " />    <toc-item title="Advanced HDL Synthesis" target="   Advanced HDL Synthesis   " />    <toc-item title="Low Level Synthesis" target="   Low Level Synthesis   " />    <toc-item title="Partition Report" target="   Partition Report     " />    <toc-item title="Final Report" target="   Final Report   " />   <view program="ngdbuild" type="Report" inputState="Synthesized" file="lpc7seg.bld" label="Translation Report" >    <toc-item title="Top of Report" target="Release" />    <toc-item title="Command Line" target="Command Line:" />    <toc-item title="Partition Status" target="Partition Implementation Status" />    <toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />   <view program="map" type="Report" inputState="Translated" file="lpc7seg_map.mrp" label="Map Report" >    <toc-item title="Section 1: Errors" target="Section 1 - " />    <toc-item title="Section 2: Warnings" target="Section 2 - " />    <toc-item title="Section 3: Infos" target="Section 3 - " />    <toc-item title="Section 4: Removed Logic Summary" target="Section 4 - " />    <toc-item title="Section 5: Removed Logic" target="Section 5 - " />    <toc-item title="Section 6: IOB Properties" target="Section 6 - " />    <toc-item title="Section 7: RPMs" target="Section 7 - " />    <toc-item title="Section 8: Guide Report" target="Section 8 - " />    <toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 - " />    <toc-item title="Section 10: Modular Design Summary" target="Section 10 - " />    <toc-item title="Section 11: Timing Report" target="Section 11 - " />    <toc-item title="Section 12: Configuration String Information" target="Section 12 - " />   <view program="par" type="Report" inputState="Mapped" file="lpc7seg.par" label="Place and Route Report" >    <toc-item title="Device Utilization" target="Device Utilization Summary:" />    <toc-item title="Placer Information" target="Starting Placer" />    <toc-item title="Router Information" target="Starting Router" />    <toc-item title="Clock Report" target="Generating Clock Report" />    <toc-item title="Timing Results" target="Timing Score:" />    <toc-item title="Final Summary" target="Peak Memory Usage:" />   <view program="trce" type="Report" inputState="Routed" file="lpc7seg.twr" label="Static Timing Report" >    <toc-item title="Data Sheet Report" target="Data Sheet" />    <toc-item title="Timing Summary" target="Timing summary:" />   <view program="bitgen" type="Report" inputState="Routed" file="lpc7seg.bgn" label="Bitgen Report" >    <toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />    <toc-item title="Final Summary" target="DRC detected" />  <viewgroup label="Secondary Reports" >   <view hidden="true" program="isim" type="Secondary_Report" inputState="PreSynthesized" file="isim.log" label="ISIM Simulator Log" />   <view hidden="true" program="map" type="Secondary_Report" inputState="Translated" file="lpc7seg_map.map" label="Map Log File" >    <toc-item title="Design Information" target="Design Information" />    <toc-item title="Design Summary" target="Design Summary" />   <view hidden="true" program="xplorer" type="Secondary_Report" inputState="Routed" file="lpc7seg_xplorer.rpt" label="Xplorer Report" />   <view hidden="true" program="netgen" type="Secondary_Report" inputState="Translated" file="netgen/translate/lpc7seg_translate.nlf" label="Post-Translate Simulation Model Report" />   <view hidden="true" program="trce" type="Secondary_Report" inputState="Mapped" file="lpc7seg_preroute.twr" label="Post-Map Static Timing Report" />   <view hidden="true" program="netgen" type="Secondary_Report" inputState="Mapped" file="netgen/map/lpc7seg_map.nlf" label="Post-Map Simulation Model Report" />   <view hidden="true" program="par" type="Pad_Report" inputState="Mapped" file="lpc7seg_pad.txt" label="Pad Report" />   <view hidden="true" program="par" type="Secondary_Report" inputState="Mapped" file="lpc7seg.unroutes" label="Unroutes Report" />   <view hidden="true" program="par" type="Secondary_Report" inputState="Mapped" file="lpc7seg.grf" label="Guide Results Report" />   <view hidden="true" program="par" type="Secondary_Report" inputState="Routed" file="lpc7seg.dly" label="Asynchronous Delay Report" />   <view hidden="true" program="par" type="Secondary_Report" inputState="Routed" file="lpc7seg.clk_rgn" label="Clock Region Report" />   <view hidden="true" program="netgen" type="Secondary_Report" inputState="Routed" file="netgen/par/lpc7seg_timesim.nlf" label="Post-Route Simulation Model Report" />   <view hidden="true" program="xpwr" type="Report" inputState="Routed" file="lpc7seg.pwr" label="Power Report" /> </body></report-views>PK

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ml" label="Partition Report" >   <view program="map" inputState="Translated" type="IOBProperties" file="lpc_7seg_map.mrp" label="IOB Properties" />   <view program="par" inputState="Mapped" type="ConstraintsData" file="lpc_7seg.par" label="Timing Constraints" />   <view program="par" inputState="Mapped" type="PinoutData" file="lpc_7seg.pad" label="Pinout Report" />   <view program="par" inputState="Mapped" type="ClocksData" file="lpc_7seg.par" label="Clock Report" />  </viewgroup>  <viewgroup label="Errors and Warnings" >   <view program="xst" type="MessageList" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" hideColumns="Filtered" />   <view program="ngdbuild" inputState="Synthesized" type="MessageList" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" hideColumns="Filtered" />   <view program="map" inputState="Translated" type="MessageList" file="_xmsgs/map.xmsgs" label="Map Messages" hideColumns="Filtered" />   <view program="par" inputState="Mapped" type="MessageList" file="_xmsgs/par.xmsgs" label="Place and Route Messages" hideColumns="Filtered" />   <view program="trce" inputState="Routed" type="MessageList" file="_xmsgs/trce.xmsgs" label="Timing Messages" hideColumns="Filtered" />   <view program="bitgen" inputState="Routed" type="MessageList" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" hideColumns="Filtered" />   <view fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/bitgen.xmsgs" program="implementation" inputState="Current" type="MessageList" file="_xmsgs/*.xmsgs" label="All Current Messages" hideColumns="Filtered" />  <viewgroup label="Detailed Reports" >   <view program="xst" type="Report" file="lpc_7seg.syr" label="Synthesis Report   " >    <toc-item title="Synthesis Options Summary" target="   Synthesis Options Summary   " />    <toc-item title="HDL Compilation" target="   HDL Compilation   " />    <toc-item title="Design Hierarchy Analysis" target="   Design Hierarchy Analysis   " />    <toc-item title="HDL Analysis" target="   HDL Analysis   " />    <toc-item title="HDL Synthesis" target="   HDL Synthesis   " />    <toc-item title="Advanced HDL Synthesis" target="   Advanced HDL Synthesis   " />    <toc-item title="Low Level Synthesis" target="   Low Level Synthesis   " />    <toc-item title="Partition Report" target="   Partition Report     " />    <toc-item title="Final Report" target="   Final Report   " />   <view program="ngdbuild" inputState="Synthesized" type="Report" file="lpc_7seg.bld" label="Translation Report" >    <toc-item title="Top of Report" target="Release" />    <toc-item title="Command Line" target="Command Line:" />    <toc-item title="Partition Status" target="Partition Implementation Status" />    <toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />   <view program="map" inputState="Translated" type="Report" file="lpc_7seg_map.mrp" label="Map Report" >    <toc-item title="Section 1: Errors" target="Section 1 - " />    <toc-item title="Section 2: Warnings" target="Section 2 - " />    <toc-item title="Section 3: Infos" target="Section 3 - " />    <toc-item title="Section 4: Removed Logic Summary" target="Section 4 - " />    <toc-item title="Section 5: Removed Logic" target="Section 5 - " />    <toc-item title="Section 6: IOB Properties" target="Section 6 - " />    <toc-item title="Section 7: RPMs" target="Section 7 - " />    <toc-item title="Section 8: Guide Report" target="Section 8 - " />    <toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 - " />    <toc-item title="Section 10: Modular Design Summary" target="Section 10 - " />    <toc-item title="Section 11: Timing Report" target="Section 11 - " />    <toc-item title="Section 12: Configuration String Information" target="Section 12 - " />   <view program="par" inputState="Mapped" type="Report" file="lpc_7seg.par" label="Place and Route Report" >    <toc-item title="Device Utilization" target="Device Utilization Summary:" />    <toc-item title="Placer Information" target="Starting Placer" />    <toc-item title="Router Information" target="Starting Router" />    <toc-item title="Clock Report" target="Generating Clock Report" />    <toc-item title="Timing Results" target="Timing Score:" />    <toc-item title="Final Summary" target="Peak Memory Usage:" />   <view program="trce" inputState="Routed" type="Report" file="lpc_7seg.twr" label="Static Timing Report" >    <toc-item title="Data Sheet Report" target="Data Sheet" />    <toc-item title="Timing Summary" target="Timing summary:" />   <view program="bitgen" inputState="Routed" type="Report" file="lpc_7seg.bgn" label="Bitgen Report" >    <toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />    <toc-item title="Final Summary" target="DRC detected" />  <viewgroup label="Secondary Reports" >   <view program="isim" hidden="true" inputState="PreSynthesized" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" />   <view program="map" hidden="true" inputState="Translated" type="Secondary_Report" file="lpc_7seg_map.map" label="Map Log File" >    <toc-item title="Design Information" target="Design Information" />    <toc-item title="Design Summary" target="Design Summary" />   <view program="xplorer" hidden="true" inputState="Routed" type="Secondary_Report" file="lpc_7seg_xplorer.rpt" label="Xplorer Report" />   <view program="netgen" hidden="true" inputState="Translated" type="Secondary_Report" file="netgen/translate/lpc_7seg_translate.nlf" label="Post-Translate Simulation Model Report" />   <view program="trce" hidden="true" inputState="Mapped" type="Secondary_Report" file="lpc_7seg_preroute.twr" label="Post-Map Static Timing Report" />   <view program="netgen" hidden="true" inputState="Mapped" type="Secondary_Report" file="netgen/map/lpc_7seg_map.nlf" label="Post-Map Simulation Model Report" />   <view program="par" hidden="true" inputState="Mapped" type="Pad_Report" file="lpc_7seg_pad.txt" label="Pad Report" />   <view program="par" hidden="true" inputState="Mapped" type="Secondary_Report" file="lpc_7seg.unroutes" label="Unroutes Report" />   <view program="par" hidden="true" inputState="Mapped" type="Secondary_Report" file="lpc_7seg.grf" label="Guide Results Report" />   <view program="par" hidden="true" inputState="Routed" type="Secondary_Report" file="lpc_7seg.dly" label="Asynchronous Delay Report" />   <view program="par" hidden="true" inputState="Routed" type="Secondary_Report" file="lpc_7seg.clk_rgn" label="Clock Region Report" />   <view program="netgen" hidden="true" inputState="Routed" type="Secondary_Report" file="netgen/par/lpc_7seg_timesim.nlf" label="Post-Route Simulation Model Report" />   <view program="xpwr" hidden="true" inputState="Routed" type="Report" file="lpc_7seg.pwr" label="Power Report" />   <view hidden="true" program="map" type="Secondary_Report" inputState="Mapped" file="lpc_7seg_map.psr" label="Physical Synthesis Report" />   <toc-item title="Physical Synthesis Options Summary" target="Physical Synthesis Options Summary" />   <toc-item title="Optimizations statistics and details" target="Optimizations statistics and details" />   <toc-item title="Preserved elements" target="Preserved elements" />   <toc-item title="Timing information" target="Timing information" /> </body></report-views>PK

__REGISTRY__/PK
__REGISTRY__/Autonym/PK
__REGISTRY__/Autonym/regkeysPK
__REGISTRY__/Cs/PK
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#__REGISTRY__/ExpandedNetlistEngine/PK
*__REGISTRY__/ExpandedNetlistEngine/regkeysPK
 __REGISTRY__/HierarchicalDesign/PK
*__REGISTRY__/HierarchicalDesign/HDProject/PK

s
CommandLine-Ngdbuild
C:\Xilinx\10.1\ISE\bin\nt\unwrapped\ngdbuild.exe -ise C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/lpc_7seg.ise -intstyle ise -dd _ngo -nt timestamp -i -p xc3s400-fg456-4 lpc_7seg.ngc lpc_7seg.ngd
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CommandLine-Par

s
CommandLine-Xst

s
Previous-NGD
lpc_7seg_prev_built.ngd
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Previous-NGM

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Previous-Packed-NCD

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Previous-Routed-NCD

s
PK
'__REGISTRY__/HierarchicalDesign/regkeysPK
__REGISTRY__/ProjectNavigator/PK
10.1
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sMigrationTypeKey
new_project
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PK
!__REGISTRY__/ProjectNavigatorGui/PK
(__REGISTRY__/ProjectNavigatorGui/regkeysPK
__REGISTRY__/STE/PK
__REGISTRY__/STE/bitgen/PK
C:\Xilinx\10.1\ISE\bin\nt\unwrapped\bitgen.exe -ise C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/lpc_7seg.ise -intstyle ise -f lpc_7seg.ut lpc_7seg.ncd
s
FormatString
bitgen [-d] [-j] [-b] [-w] [-l] [-m] [-t] [-n] [-u] [-a] [--p] [-r <bitFile>] [-intstyle ise|xflow|silent] [-ise <projectrepositoryfile>] {-bd <BRAM_data_file> [tag <tagname>]} {-g <setting_value>} <infile[.ncd]> [<outfile>] [<pcffile[.pcf]>]
s
PK
__REGISTRY__/STE/map/PK
C:\Xilinx\10.1\ISE\bin\nt\unwrapped\map.exe -ise C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/lpc_7seg.ise -intstyle ise -p xc3s400-fg456-4 -cm area -pr b -k 4 -c 100 -o lpc_7seg_map.ncd lpc_7seg.ngd lpc_7seg.pcf
s
FormatString
map <infile[.ngd]> [-bp] [-c [<packfactor:0,100>]] [-cm <covermode>] [-detail] [-equivalent_register_removal on|off] [-global_opt off|&speed|&area|on] [-ignore_keep_hierarchy] [-intstyle ise|xflow|silent] [-ir] [-ise <iseProjectFile>] [-k 4|5|6|7|8] [-l] [-lc off|area|auto] [-logic_opt off|on] [-ntd] [-o <outfile[.ncd]>] [-ol std|med|high] [-p <partname>] [-power off|on] [-activityfile <activityfile[.vcd|.saif]>] [-pr off|i|o|b] [-r] [-register_duplication [off|on]] [-retiming off|on] [-smartguide <guide[.ncd]>] [-t <costtable:1,100>] [-timing] [-tx on|off|aggressive|limit] [-u]  [-w]  [-x]  [-xe c|n] [--ds <doodlescript>] [--hv] [--lambda <inputlambda:1,15> <outputlambda:1,4>] [--m]  [--ms <mapscript>] [--physical_synthesis off|on] [--smartsynthesis <value>] [--ts_comb <combll> <combul>] [--ts_cy <cyll> <cyul>] [--ts_load <load>] [--ts_trigger <trigger>] [--use_soft_locs] [--global_opt_script <file>] [<prffile[.pcf]>]
s
PK
__REGISTRY__/STE/ngdbuild/PK
C:\Xilinx\10.1\ISE\bin\nt\unwrapped\ngdbuild.exe -ise C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/lpc_7seg.ise -intstyle ise -dd _ngo -nt timestamp -i -p xc3s400-fg456-4 lpc_7seg.ngc lpc_7seg.ngd
s
FormatString
ngdbuild [-p <partname>] {-sd <source_dir>} {-l <library>} [-ur <rules_file[.urf]>] [-dd <output_dir>] [-r] [-a] [-u] [-nt timestamp|on|off] [-uc <ucf_file[.ucf]>] [-aul] [-bm <bmm_file[.bmm]>] [-i] [-modular initial|module|assemble] [-intstyle ise|xflow|silent] [-quiet] [-verbose] [-active <active_module_name>] [-pimpath <pimpath>] {-use_pim <pim_module_name>} [-insert_keep_hierarchy] [--forcengd] {--n <ngl_file>} {--sl <library>} [--global_opt] [--script <tcl_file>] [--incremental] [--csttrans] <design_name> [<ngd_file[.ngd]>]
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PK
__REGISTRY__/STE/par/PK
C:\Xilinx\10.1\ISE\bin\nt\unwrapped\par.exe -ise C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/lpc_7seg.ise -w -intstyle ise -ol std -t 1 lpc_7seg_map.ncd lpc_7seg.ncd lpc_7seg.pcf
s
FormatString
par [-ol std|med|high] [-pl std|med|high] [-rl std|med|high] [-xe n|c] [-t <costtable:1,100>] [-p] [-k] [-r] [-w] [-smartguide <guidefile[.ncd]>] [-n <iterations:0,100>] [-s <savebest:1,100>] [-m <nodelistfile>] [-x] [-ub] [-nopad] [-power on|off] [-activityfile <activityfile[.vcd|.saif]>] [-ntd] [-intstyle ise|xflow|silent] [-ise <projectrepositoryfile>] [--strategy use_placement|keep_placement|ignore_placement]<infile[.ncd]> <outfile> [<constraintsfile[.pcf]>]
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PK
__REGISTRY__/STE/trce/PK
C:/Xilinx/10.1/ISE/bin/nt/unwrapped/trce.exe -ise C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/lpc_7seg.ise -intstyle ise -e 3 -s 4 -xml lpc_7seg lpc_7seg.ncd -o lpc_7seg.twr lpc_7seg.pcf -ucf lpc_7seg.ucf
s
FormatString
trce.exe ([-e|-v [<limit:0,2000000000>]] [-l <limit:0,2000000000>] [-n [<limit:0,2000000000>]] [-u [<limit:0,2000000000>]] [-skew] [-a] [--p] [-s <speed>] [-o <report[.twr]>] [--m] [-stamp <stampfile>] [-tsi <tsifile[.tsi]>] [-xml <report[.twx]>] [-nodatasheet] [-timegroups] [-fastpaths] [-intstyle ise|xflow|silent] [-ise <projectfile>] [--ucf <constraint[.ucf]>] <design[.ncd]> [<constraint[.pcf]>]) | ([-run <macro[.xtm]> [<design[.ncd]> [<constraint[.pcf]>]]] [-intstyle ise|xflow|silent] [-ise <projectfile>])
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PK
__REGISTRY__/STE/xst/PK
C:\Xilinx\10.1\ISE\bin\nt\unwrapped\xst.exe -ise C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/lpc_7seg.ise -intstyle ise -ifn C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/lpc_7seg.xst -ofn C:/hharte/work/HarteTec/cores/wb_lpc/examples/lpc_7seg/lpc_7seg.syr -finalclean 1
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FormatString
xst [-ifn <InputFile>] [-ofn <OutputFile>] [-ise <iseProjectFile>] [--quiet] [-intstyle <Style>] [--deb <DebugLevel>] [--finalclean <Clean>] [--PcubeFlow] [--globOptFlow] [--XstNtrc]
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PK
Co//__REGISTRY__/STE/regkeysMostRecentClient
bitgen
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SteInfoVersion
0.0
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PK
__REGISTRY__/SrcCtrl/PK
__REGISTRY__/SrcCtrl/regkeysPK
__REGISTRY__/XSLTProcess/PK
_xmsgs/XSLTProcess.xmsgs
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PK
 __REGISTRY__/_ProjRepoInternal_/PK
9.1.03i
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ISE_VERSION_LAST_SAVED_WITH
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LastRepoDir
C:\hharte\work\HarteTec\cores\wb_lpc\examples\lpc_7seg\
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OBJSTORE_VERSION
1.3
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PROJECT_CREATION_TIMESTAMP
UNINITIALIZED
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REGISTRY_VERSION
1.1
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REPOSITORY_VERSION
1.1
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PK
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_xmsgs/bitgen.xmsgs
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PK
__REGISTRY__/common/PK
false
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MessageCaptureEnabled
true
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MessageFilterFile
filter.filter
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MessageFilteringEnabled
false
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RunOnce
#/PnAutoRun/Scripts/RunOnce_tcl
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PK
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_xmsgs/cpldfit.xmsgs
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PK
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_xmsgs/dumpngdio.xmsgs
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PK
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PK
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PK
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_xmsgs/map.xmsgs
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PK
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_xmsgs/netgen.xmsgs
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PK
__REGISTRY__/ngc2edif/PK
OUś00__REGISTRY__/ngc2edif/regkeysClientMessageOutputFile
_xmsgs/ngc2edif.xmsgs
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PK
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_xmsgs/ngcbuild.xmsgs
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_xmsgs/par.xmsgs
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_xmsgs/runner.xmsgs
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_xmsgs/taengine.xmsgs
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PK
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,,__REGISTRY__/trce/regkeysClientMessageOutputFile
_xmsgs/trce.xmsgs
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PK
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ISE_VERSION_LAST_SAVED_WITH
10.1