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<h1>Wishbone Monitor Controller Central Core</h1>
<h2>Description</h2>
<strong>Wishbone Monitor Controller</strong> is a set of freely available VHDL cores. It contains
a central building block containing the basic functionality. This core comprises of a
sync generator, a pixel data generator, a memory interface and a CPU interface. These functions
of course implemented in separate entities but this is the smallest fully functional building-block
of the Wishbone Monitor Controller project. The functionality of this module can then be expanded
by adding external modules.
<p>
The Wishbone Monitor Cotroller Central Core is 100% Wishbone compatible with the 
<a href="/cores/wb_tk/wb_extensions.shtml">WishboneTK extensions</a>. It incorporates 3
Wishbone interfaces. One salve interface for register accesses another slave interface for
pixel memory accesses and one master interface for the pixel memory. Arbitation between
the core and the external master accessing the pixel memory handled by the core internally.
 
<h2>Features</h2>
<ul>
	<li>Highly customizable sync generation with polarity control</li>
	<li>Capable of driving EGA/VGA/Hercules/CGA monitors</li>
	<li>Multi-scan support for low resolution modes</li>
	<li>Internal memory for multi-scan, for even less memory accesses</li>
	<li>FIFO de-coupled memory interface and pixel output circuit</li>
	<li>Wisbone pixel memory interface</li>
	<li>16-bit pixel memory support (later parametrizable)</li>
	<li>Programmable color depth (1,2,4,8 bits per pixel)</li>
	<li>~80Mhz pixel clock (wish)</li>
	<li>Standard parametrizable Wishbone CPU bus interface</li>
	<li>Syncron internal structure</li>
	<li>Fully synthesizable (using Leonardo Spectrum)</li>
</ul>
 
<h3>Wishbone datasheet</h3>
<table border>
<tr><th>Description</th><th>Specification</th></tr>
<tr><td>General Description             </td><td>Monitor controller central core.</td></tr>
<tr><td>Supported cycles                </td><td>Slave read/write<br>Slave block read/write<br>Slave rmw<br>
												 Master read/write<br>Master block read/write<br>Master rmw<br></td></tr>
<tr><td>Data port size                  </td><td>Configurable on slave side, 16-bits on the master side</td></tr>
<tr><td>Data port granularity           </td><td>8-bit</td></tr>
<tr><td>Data port maximum operand size  </td><td>Bus size</td></tr>
<tr><td>Data transfer ordering          </td><td>Little endien</td></tr>
<tr><td>Data transfer sequencing        </td><td>n/a</td></tr>
<tr><td>Supported signal list and cross reference to equivalent Wishbone signals</td><td>
	<table>
	<tr><th>Signal name</th><th>Wishbone equiv.</th></tr>
	<tr><th colspan="2">Common signals for all ports</th></tr>
	<tr><td>CLK_I       </td><td>CLK_I</td></tr>
	<tr><td>RST_I       </td><td>RST_I</td></tr>
	<tr><th colspan="2">Signals for pixel memory master</th></tr>
	<tr><td>VMEM_CYC_I       </td><td>CYC_I</td></tr>
	<tr><td>VMEM_STB_I       </td><td>STB_I</td></tr>
	<tr><td>VMEM_WE_I        </td><td>WE_I </td></tr>
	<tr><td>VMEM_ACK_O       </td><td>ACK_O</td></tr>
	<tr><td>VMEM_SEL_I(..)   </td><td>SEL_I()</td></tr>
	<tr><td>VMEM_ADR_I(..)   </td><td>ADR_I()</td></tr>
	<tr><td>VMEM_DAT_I(..)   </td><td>DAT_I()</td></tr>
	<tr><td>VMEM_DAT_O(..)   </td><td>DAT_O()</td></tr>
	<tr><th colspan="2">Signals for register master</th></tr>
	<tr><td>REG_CYC_I       </td><td>CYC_I</td></tr>
	<tr><td>REG_STB_I       </td><td>STB_I</td></tr>
	<tr><td>REG_WE_I        </td><td>WE_I </td></tr>
	<tr><td>REG_ACK_O       </td><td>ACK_O</td></tr>
	<tr><td>REG_SEL_I(..)   </td><td>SEL_I()</td></tr>
	<tr><td>REG_ADR_I(..)   </td><td>ADR_I()</td></tr>
	<tr><td>REG_DAT_I(..)   </td><td>DAT_I()</td></tr>
	<tr><td>REG_DAT_O(..)   </td><td>DAT_O()</td></tr>
	<tr><th colspan="2">Signals to connect to the pixel memory</th></tr>
	<tr><td>V_CYC_O       </td><td>CYC_O</td></tr>
	<tr><td>V_STB_O       </td><td>STB_O</td></tr>
	<tr><td>V_WE_O        </td><td>WE_O </td></tr>
	<tr><td>V_ACK_I       </td><td>ACK_I</td></tr>
	<tr><td>V_SEL_O(..)   </td><td>SEL_O()</td></tr>
	<tr><td>V_ADR_O(..)   </td><td>ADR_O()</td></tr>
	<tr><td>V_DAT_I(..)   </td><td>DAT_I()</td></tr>
	<tr><td>V_DAT_O(..)   </td><td>DAT_O()</td></tr>
	</table>
</table>
<h3>Parameter description</h3>
<table border>
<tr><td>Parameter name</th><th>Description</th></tr>
<tr><td>v_dat_width   </td><td>Pixel memory data width</td></tr>
<tr><td>v_adr_width   </td><td>Pixel memory address width</td></tr>
<tr><td>cpu_dat_width </td><td>CPU data width</td></tr>
<tr><td>cpu_adr_width </td><td>Pixel memory access interface address width</td></tr>
<tr><td>reg_adr_width </td><td>Register access interface address width</td></tr>
<tr><td>fifo_size     </td><td>Size of the internal FIFO buffers in <code>v_dat_width</code> bits</td></tr>
</table>
<h3>Signal description</h3>
<table border>
<tr><th>Signal name</th><th>Description</th></tr>
<tr><th colspan="2">Signals to connect to the pixel memory master</th></tr>
<tr><td>VMEM_CYC_I       </td><td>Wishbone cycle signal. High value frames blocks of access</td></tr>
<tr><td>VMEM_STB_I       </td><td>Wishbone strobe signal. High value indicates cycle to this particular device</td></tr>
<tr><td>VMEM_WE_I        </td><td>Wishbone write enable signal. High indicates data flowing from master to slave</td></tr>
<tr><td>VMEM_ACK_O       </td><td>Wishbone acknowledge signal. High indicates that slave finished operation sucessfully</td></tr>
<tr><td>VMEM_ACK_OI      </td><td>WhisboneTK acknowledge chain input signal</td></tr>
<tr><td>VMEM_ADR_I(cpu_adr_width-1..0)  </td><td>Wishbone address bus signals</td></tr>
<tr><td>VMEM_SEL_I(cpu_dat_width/8-1..0) </td><td>Wishbone byte-selection signals</td></tr>
<tr><td>VMEM_DAT_I(cpu_dat_width-1..0)   </td><td>Wishbone data bus input (to slave direction) signals</td></tr>
<tr><td>VMEM_DAT_O(cpu_dat_width-1..0)   </td><td>Wishbone data bus output (to master direction) signals</td></tr>
<tr><td>VMEM_DAT_OI(cpu_dat_width-1..0)  </td><td>WhisboneTK data bus chain input signal</td></tr>
<tr><th colspan="2">Signals to connect to the register master</th></tr>
<tr><td>REG_CYC_I       </td><td>Wishbone cycle signal. High value frames blocks of access</td></tr>
<tr><td>REG_STB_I       </td><td>Wishbone strobe signal. High value indicates cycle to this particular device</td></tr>
<tr><td>REG_WE_I        </td><td>Wishbone write enable signal. High indicates data flowing from master to slave</td></tr>
<tr><td>REG_ACK_O       </td><td>Wishbone acknowledge signal. High indicates that slave finished operation sucessfully</td></tr>
<tr><td>REG_ACK_OI      </td><td>WhisboneTK acknowledge chain input signal</td></tr>
<tr><td>REG_ADR_I(reg_adr_width-1..0)  </td><td>Wishbone address bus signals</td></tr>
<tr><td>REG_SEL_I(cpu_dat_width/8-1..0) </td><td>Wishbone byte-selection signals</td></tr>
<tr><td>REG_DAT_I(cpu_dat_width-1..0)   </td><td>Wishbone data bus input (to slave direction) signals</td></tr>
<tr><td>REG_DAT_O(cpu_dat_width-1..0)   </td><td>Wishbone data bus output (to master direction) signals</td></tr>
<tr><td>REG_DAT_OI(cpu_dat_width-1..0)  </td><td>WhisboneTK data bus chain input signal</td></tr>
<tr><th colspan="2">Signals to connect to the pixel memory</th></tr>
<tr><td>V_CYC_O       </td><td>Wishbone cycle signal. High value frames blocks of access</td></tr>
<tr><td>V_STB_O       </td><td>Wishbone strobe signal. High value indicates cycle to this particular device</td></tr>
<tr><td>V_WE_O        </td><td>Wishbone write enable signal. High indicates data flowing from master to slave</td></tr>
<tr><td>V_ACK_I       </td><td>Wishbone acknowledge signal. High indicates that slave finished operation sucessfully</td></tr>
<tr><td>V_ADR_O(m_addr_width-2..0)  </td><td>Wishbone address bus signals</td></tr>
<tr><td>V_SEL_O(s_bus_width/8-1..0) </td><td>Wishbone byte-selection signals</td></tr>
<tr><td>V_DAT_I(s_bus_width-1..0)   </td><td>Wishbone data bus input (to slave direction) signals</td></tr>
<tr><td>V_DAT_O(s_bus_width-1..0)   </td><td>Wishbone data bus output (to master direction) signals</td></tr>
<tr><th colspan="2">Non Wishbone signals</th></tr>
<tr><td>H_SYNC    </td><td>Horizontal sync pulse. Active level programmable.</td></tr>
<tr><td>H_BLANK   </td><td>Horizontal blank pulse. Active level programmable.</td></tr>
<tr><td>V_SYNC    </td><td>Vertical sync pulse. Active level programmable.</td></tr>
<tr><td>V_BLANK   </td><td>Vertical blank pulse. Active level programmable.</td></tr>
<tr><td>H_TC      </td><td>Horizontal terminal count. Active high signal, active for one clock cycle/line</td></tr>
<tr><td>V_TC      </td><td>Vertical terminal count. Active high signal, active for one clock cycle/refresh</td></tr>
<tr><td>BLANK     </td><td>Blank signal. Active high signal.</td></tr>
<tr><td>VIDEO_OUT(7 downto 0) </td><td>8-bit video output. If bit-depth is less than 8, value is right alligned and padded with 0s.</td></tr>
</table>
 
<h2>Register description</h2>
<p>
The core has several programmable registers which control its behaviour. All registers can be written and checked. All registers reset to 0. 
It is recomended that the enable bit turned off prior any write to any of the registers and than enable bit turned off after all registers
are programmed to their new values. Registers are shown in 8-bit layout however the actual grouping of registers into access units depending
on the bus-width of the CPU interface. Address-decoding is allways little-endien.
 
<table border>
 
<tr><th>Offset</th><th colspan="8">Bit number</th><th>Description</th></tr>
<tr><th></th><th>7</th><th>6</th><th>5</th><th>4</th><th>3</th><th>2</th><th>1</th><th>0</th><th></th></tr>
<tr><th>0</th><td colspan="8" rowspan="4">V_MEM_END</td><td rowspan="4">Last location in the memory being part of the frame buffer. Counted in <code>v_dat_width</code> units.</th></tr>
<tr><th>1</th></tr>
<tr><th>2</th></tr>
<tr><th>3</th></tr>
<tr><th>4</th><td colspan="8" rowspan="4">V_MEM_START</td><td rowspan="4">First location in the memory being part of the frame buffer. Counted in <code>v_dat_width</code> units.</th></tr>
<tr><th>5</th></tr>
<tr><th>6</th></tr>
<tr><th>7</th></tr>
<tr><th></th><th>7</th><th>6</th><th>5</th><th>4</th><th>3</th><th>2</th><th>1</th><th>0</th><th></th></tr>
<tr><th>8</th><td colspan="8" rowspan="8"><i>reserved</i></td></tr>
<tr><th>9</th></tr>
<tr><th>10</th></tr>
<tr><th>11</th></tr>
<tr><th>12</th></tr>
<tr><th>13</th></tr>
<tr><th>14</th></tr>
<tr><th>15</th></tr>
<tr><th></th><th>7</th><th>6</th><th>5</th><th>4</th><th>3</th><th>2</th><th>1</th><th>0</th><th></th></tr>
<tr><th>16</th><td colspan="8">FIFO_TRESHOLD</td><td>Number of words in the internal pixel FIFO after pixel memory access priority changes.</tr>
<tr><th>17</th><td colspan="2"><i>res.</i></td><td colspan="2">MSS</td><td colspan="2"><i>res.</i></td><td colspan="2">BPP</td><td>MSS: Multi-scan-select. If 0 multi-scan feature is disabled.<br>
                                                                                                                                   BSS: Bits per pixel. 00 - 1 bpp, 01 - 2 bpp, 10 - 4 bpp, 11 - 8 bpp</tr>
<tr><th>18</th><td colspan="8">HBS</td><td>Horizontal blank start in 8 pixels. (Horizontal resolution)</td></tr>
<tr><th>19</th><td colspan="8">HSS</td><td>Horizontal sync pulse start in 8 pixels.</td></tr>
<tr><th>20</th><td colspan="8">HSE</td><td>Horizontal sync pulse end in 8 pixels.</td></tr>
<tr><th>21</th><td colspan="8">HTOTAL</td><td>Horizontal line total length in 8 pixels.</td></tr>
<tr><th>22</th><td colspan="8">VBS</td><td>Vertical blank start in 8 lines. (Vertical resolution)</td></tr>
<tr><th>23</th><td colspan="8">VSS</td><td>Vertical sync pulse start in 8 lines.</td></tr>    
<tr><th></th><th>7</th><th>6</th><th>5</th><th>4</th><th>3</th><th>2</th><th>1</th><th>0</th><th></th></tr>
<tr><th>24</th><td colspan="8">VSE</td><td>Vertical sync pulse end in 8 lines.</td></tr>      
<tr><th>25</th><td colspan="8">VTOTAL</td><td>Vertical total screen size in 8 lines.</td></tr>
<tr><th>26</th><td colspan="8">PSS</td><td>Pixel pre-scaler: Pixel-clock := System-clock/(PSS+1).</tr>
<tr><th>27</th><td>EN</td><td colspan="3"><i>res.</i></td><td>VBP</td><td>HBP</td><td>VSP</td><td>HSP</td>
                        <td>EN: 1 - normal operation, 0 - core is in reset state<br>
                            HSP: 0 - positive h sync, 1 - negative h sync<br>
            				VSP: 0 - positive v sync, 1 - negative v sync<br>
            				HBP: 0 - positive h blank, 1 - negative h blank<br>
            				VBP: 0 - positive v blank, 1 - negative v blank</td></tr>
<tr><th>28</th><td colspan="8" rowspan="4"><i>reserved</i></td></tr>
<tr><th>29</th></tr>
<tr><th>30</th></tr>
<tr><th>31</th></tr>
<tr><th></th><th>7</th><th>6</th><th>5</th><th>4</th><th>3</th><th>2</th><th>1</th><th>0</th><th></th></tr>
</table>
 
<h2>Features explained</h2>
<h3>Capable of driving EGA/VGA/Hercules/CGA monitors</h3>
<p>
Of course the FPGA cannot provide the correct signal levels not to mention the analog output 
required by VGA monitors. This statement means that all the necessary sync signals can be
generated.
<h3>Multi-scan support for low resolution modes</h3>
<p>
On VGA monitors low resolution modes (320x200, 320x240) are generated with this feature. Each 
video memory line scanned twice, so the physical screen will contain 400/480 scan-lines.
<h3>FIFO de-coupled memory interface and pixel output circuit</h3>
<p>
The use of FIFO buffer allows long bursts from the CPU without being interrupted by the pixel 
generation engine. It also somewhat relaxes memory speed requirements as FIFO-fill cycles can
continue through blanking periods.
<h3>16-bit pixel memory support</h3>
<p>
This device is designed to be simple and easy to use. It's not about using many megs of 
frame-buffer. The optimal size of the frame-buffer would be around 64kWords. Such a size
of memory can most easily be constructed from SRAM chips. They are also faster and easier
to interface to than DRAM let alone SDRAM devices. An external Wishbone bus interface should
be used to interface the core to the pixel memory so any memory type that has such an interface
can be used. For SRAM devices the WisboneTK 
<a href="/cores/wb_tk/wb_async_slave.shtml">Asyncronous slave interface</a> in a practical choice.
<h3>~80Mhz pixel clock</h3>
<p>
Depends of course on technology but this is the minimum to support reasonable resolutions with
usable refresh-rates.
 
<h2>Author & Maintainer</h2>
<p>
<a href="/people/tantos">Andras Tantos</a>
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