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https://opencores.org/ocsvn/wbddr3/wbddr3/trunk
Subversion Repositories wbddr3
[/] [wbddr3/] [trunk/] [Makefile] - Rev 9
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################################################################################
##
## Filename: Makefile
##
## Project: A wishbone controlled DDR3 SDRAM memory controller.
##
## Purpose: To coordinate the master build of the project. This includes
## the Verilator simulation, the test bench, and then the run of
## the testbench itself.
##
## Creator: Dan Gisselquist, Ph.D.
## Gisselquist Technology, LLC
##
################################################################################
##
## Copyright (C) 2015-2016, Gisselquist Technology, LLC
##
## This program is free software (firmware): you can redistribute it and/or
## modify it under the terms of the GNU General Public License as published
## by the Free Software Foundation, either version 3 of the License, or (at
## your option) any later version.
##
## This program is distributed in the hope that it will be useful, but WITHOUT
## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with this program. (It's in the $(ROOT)/doc directory, run make with no
## target there if the PDF file isn't present.) If not, see
## <http://www.gnu.org/licenses/> for a copy.
##
## License: GPL, v3, as defined and found on www.gnu.org,
## http://www.gnu.org/licenses/gpl.html
##
##
################################################################################
##
##
all: rtl bench test
.PHONY: doc
doc:
cd doc; $(MAKE) --no-print-directory
.PHONY: rtl
rtl:
cd rtl; $(MAKE) --no-print-directory
.PHONY: bench
bench:
cd bench/cpp; $(MAKE) --no-print-directory wbddr3_tb
.PHONY: test
test:
cd bench/cpp; $(MAKE) --no-print-directory test
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