Subversion Repositories wbddr3

# Description

The purpose of this core is to provide a GPL wishbone core capable of commanding
a DDR3 memory, such as the one used on Digilent's Arty board, at full speed. 
A particular design goal is that consecutive reads or writes should take only one additional clock cycle per read or write.  My eventual goal is to build this so that it will support my OpenArty project.

Since the DDR3 memory specification is dated August, 2009, memory chips have
been built to this specification.  However, since the DDR3 SDRAM's are rather
complex, and there is a lot of work required to manage them, controllers for
DDR3 SDRAM's are primarily in the realm of proprietary.

The lack of a good open source DDR3 SDRAM controller leaves an FPGA engineer
with the choice of building a controller for a very complex interface from
scratch, or accepting a less than optimal controller built by Xilinx's Memory
Interface Generator and then converting the result to an open source bus, such
as the wishbone.

This core is designed to meet that need: it is both open (GPL), as well as
wishbone compliant.  Further, this core offers 32-bit granularity to an interface that would otehrwise offer only 128-bit granularity.  This core also offers complete pipelined performance.  Because of the pipeline interface, this core is
appropriate for filling cache linse.  Because the core also offers non-pipelined
performance, it is also appropriate for random access from a CPU--whether by a
write-through cache, or a CPU working without a cache.

# Current status

As anyone knows who has worked with DDR3 memory controllers will know, this is
a difficult and complex project.  There are lots of parts and pieces to is.
Currently, a large portion (not all) of the Verilog code has been built,
together with what should be a very thorough Verilator test bench.  The
Verilator code successfully brings the memory out of a reset condition, and
runs it through a variety of paces.

So, today, the code works within Verilator and appears to match the
specification of the DDR3 bus.

The core does not (yet) work on any physical hardware.  This task remains.