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[/] [wbddr3/] [trunk/] [bench/] [cpp/] [pddrsim.cpp] - Rev 20
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//////////////////////////////////////////////////////////////////////////////// // // Filename: pddrsim.cpp // // Project: A wishbone controlled DDR3 SDRAM memory controller. // // Purpose: To expand a DDR3 SDRAM controllers influence across multiple // clocks. Hence, if the DDR3 SDRAM controller runs at half // the clock rate of the DDR3-SDRAM, this will expand it to the full // clock rate. // // Creator: Dan Gisselquist, Ph.D. // Gisselquist Technology, LLC // //////////////////////////////////////////////////////////////////////////////// // // Copyright (C) 2016, Gisselquist Technology, LLC // // This program is free software (firmware): you can redistribute it and/or // modify it under the terms of the GNU General Public License as published // by the Free Software Foundation, either version 3 of the License, or (at // your option) any later version. // // This program is distributed in the hope that it will be useful, but WITHOUT // ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License // for more details. // // You should have received a copy of the GNU General Public License along // with this program. (It's in the $(ROOT)/doc directory, run make with no // target there if the PDF file isn't present.) If not, see // <http://www.gnu.org/licenses/> for a copy. // // License: GPL, v3, as defined and found on www.gnu.org, // http://www.gnu.org/licenses/gpl.html // // //////////////////////////////////////////////////////////////////////////////// // // #include <stdio.h> #include <stdlib.h> #include "ddrsdramsim.h" #include "pddrsim.h" void PDDRSIM::operator()(int reset_n, int cke, int busoe, unsigned cmda, unsigned cmdb, unsigned cmdc, unsigned cmdd, const unsigned *data_to_sdram, unsigned *data_from_sdram) { int csn, rasn, casn, wen, dqs, dm, odt, addr, ba; csn = (cmda >> 26)&1; rasn = (cmda >> 25)&1; casn = (cmda >> 24)&1; wen = (cmda >> 23)&1; ba = (cmda >> 20)&0x7; // 3 bits addr = (cmda >> 6)&0x3fff; // 14 bits dqs = (cmda >> 5)&0x01; // 1 bits dm = (cmda >> 1)&0x0f; // 4 bits odt = (cmda )&0x01; // 1 bits data_from_sdram[0] = DDRSDRAMSIM::apply( reset_n, cke, csn, rasn, casn, wen, dqs, dm, odt, busoe, addr, ba, data_to_sdram[0]); csn = (cmdb >> 26)&1; rasn = (cmdb >> 25)&1; casn = (cmdb >> 24)&1; wen = (cmdb >> 23)&1; ba = (cmdb >> 20)&0x7; // 3 bits addr = (cmdb >> 6)&0x3fff; // 14 bits dqs = (cmdb >> 5)&0x01; // 1 bits dm = (cmdb >> 1)&0x0f; // 4 bits odt = (cmdb )&0x01; // 1 bits data_from_sdram[1] = DDRSDRAMSIM::apply( reset_n, cke, csn, rasn, casn, wen, dqs, dm, odt, busoe, addr, ba, data_to_sdram[1]); csn = (cmdc >> 26)&1; rasn = (cmdc >> 25)&1; casn = (cmdc >> 24)&1; wen = (cmdc >> 23)&1; ba = (cmdc >> 20)&0x7; // 3 bits addr = (cmdc >> 6)&0x3fff; // 14 bits dqs = (cmdc >> 5)&0x01; // 1 bits dm = (cmdc >> 1)&0x0f; // 4 bits odt = (cmdc )&0x01; // 1 bits data_from_sdram[2] = DDRSDRAMSIM::apply( reset_n, cke, csn, rasn, casn, wen, dqs, dm, odt, busoe, addr, ba, data_to_sdram[2]); csn = (cmdd >> 26)&1; rasn = (cmdd >> 25)&1; casn = (cmdd >> 24)&1; wen = (cmdd >> 23)&1; ba = (cmdd >> 20)&0x7; // 3 bits addr = (cmdd >> 6)&0x3fff; // 14 bits dqs = (cmdd >> 5)&0x01; // 1 bits dm = (cmdd >> 1)&0x0f; // 4 bits odt = (cmdd )&0x01; // 1 bits data_from_sdram[3] = DDRSDRAMSIM::apply( reset_n, cke, csn, rasn, casn, wen, dqs, dm, odt, busoe, addr, ba, data_to_sdram[3]); }
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