URL
https://opencores.org/ocsvn/wbddr3/wbddr3/trunk
Subversion Repositories wbddr3
[/] [wbddr3/] [trunk/] [rtl/] [Makefile] - Rev 18
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################################################################################
##
## Filename: Makefile
##
## Project: A wishbone conrolled DDR3 SDRAM controller.
##
## Purpose: To direct the Verilator build of our one source file. The
## result will be a library, Vwbddrsdram__ALL.a, found and kept
## in the obj_dir/ subdirectory.
##
##
## Creator: Dan Gisselquist, Ph.D.
## Gisselquist Technology, LLC
##
################################################################################
##
## Copyright (C) 2015, Gisselquist Technology, LLC
##
## This program is free software (firmware): you can redistribute it and/or
## modify it under the terms of the GNU General Public License as published
## by the Free Software Foundation, either version 3 of the License, or (at
## your option) any later version.
##
## This program is distributed in the hope that it will be useful, but WITHOUT
## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## License: GPL, v3, as defined and found on www.gnu.org,
## http:##www.gnu.org/licenses/gpl.html
##
##
################################################################################
##
##
all: wbddrsdram
YYMMDD=`date +%Y%m%d`
CXX := g++
FBDIR := .
SOURCES:= wbddrsdram.v
VDIRFB:= $(FBDIR)/obj_dir
.PHONY: wbddrsdram
wbddrsdram: $(VDIRFB)/Vwbddrsdram__ALL.a
$(VDIRFB)/Vwbddrsdram__ALL.a: $(VDIRFB)/Vwbddrsdram.h $(VDIRFB)/Vwbddrsdram.cpp
$(VDIRFB)/Vfastmaster__ALL.a: $(VDIRFB)/Vwbddrsdram.mk
$(VDIRFB)/Vwbddrsdram.h $(VDIRFB)/wbddrsdram.cpp $(VDIRFB)/wbddrsdram.mk: $(SOURCES)
$(VDIRFB)/V%.cpp $(VDIRFB)/V%.h $(VDIRFB)/V%.mk: $(FBDIR)/%.v
verilator -cc $*.v
$(VDIRFB)/V%__ALL.a: $(VDIRFB)/V%.mk
cd $(VDIRFB); make -f V$*.mk
.PHONY: clean
clean:
rm -rf $(VDIRFB)/*.mk
rm -rf $(VDIRFB)/*.cpp
rm -rf $(VDIRFB)/*.h
rm -rf $(VDIRFB)/
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