URL
https://opencores.org/ocsvn/wbddr3/wbddr3/trunk
Subversion Repositories wbddr3
[/] [wbddr3/] [trunk/] [rtl/] [xoddrserdes.v] - Rev 18
Go to most recent revision | Compare with Previous | Blame | View Log
//////////////////////////////////////////////////////////////////////////////// // // Filename: xoddrserdes.v // // Project: A wishbone controlled DDR3 SDRAM memory controller. // // Purpose: Provide DDR outputs at 8x the clock rate (with a 4x clock given) // for such things as the memory clock output, and the data strobe // output (DQS) which needs to be synchronous with the memory clock output. // // Creator: Dan Gisselquist, Ph.D. // Gisselquist Technology, LLC // //////////////////////////////////////////////////////////////////////////////// // // Copyright (C) 2015-2016, Gisselquist Technology, LLC // // This program is free software (firmware): you can redistribute it and/or // modify it under the terms of the GNU General Public License as published // by the Free Software Foundation, either version 3 of the License, or (at // your option) any later version. // // This program is distributed in the hope that it will be useful, but WITHOUT // ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License // for more details. // // You should have received a copy of the GNU General Public License along // with this program. (It's in the $(ROOT)/doc directory, run make with no // target there if the PDF file isn't present.) If not, see // <http://www.gnu.org/licenses/> for a copy. // // License: GPL, v3, as defined and found on www.gnu.org, // http://www.gnu.org/licenses/gpl.html // // //////////////////////////////////////////////////////////////////////////////// // // module xoddrserdes(i_clk_fast, i_clk_slow, i_reset, i_data, o_pin); input i_clk_fast, i_clk_slow, i_reset; input [7:0] i_data; output o_pin; wire local_monitor_pin__unconnected; wire oe_for_fabric__unconnected; wire [1:0] local_shiftout__unconnected; wire local_tbyte_out__unconnected; wire send_to_iob; wire oe_for_iob; OSERDESE2 #( .DATA_RATE_OQ("DDR"), .DATA_RATE_TQ("BUF"), .DATA_WIDTH(8), // 8 data wires sent per clkdiv .INIT_OQ(1'b1), .SERDES_MODE("MASTER"), // .TRISTATE_WIDTH(1), .INIT_TQ(1'b1), .TBYTE_CTL("FALSE"), .TBYTE_SRC("FALSE") ) oserdes_i( .CLK(i_clk_fast), .CLKDIV(i_clk_slow), .OCE(1'b1), .OFB(local_monitor_pin__unconnected), .OQ(send_to_iob), .RST(i_reset), // .TCE(1'b1), .TQ(oe_for_iob), .TFB(oe_for_fabric__unconnected), .T1(1'b0), .T2(1'b0), .T3(1'b0), .T4(1'b0), // .SHIFTOUT1(local_shiftout__unconnected[0]), .SHIFTOUT2(local_shiftout__unconnected[1]), .SHIFTIN1(1'b0), .SHIFTIN2(1'b0), .TBYTEIN(1'b0), .TBYTEOUT(local_tbyte_out__unconnected), // // And now for the actual data we wish to send // .D1(i_data[0]), .D2(i_data[1]), .D3(i_data[2]), .D4(i_data[3]), .D5(i_data[4]), .D6(i_data[5]), .D7(i_data[6]), .D8(i_data[7]) ); OBUF iobuf_i(.I(send_to_iob), .O(o_pin)); endmodule
Go to most recent revision | Compare with Previous | Blame | View Log