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[/] [wbuart32/] [trunk/] [bench/] [formal/] [rxuartlite.ys] - Rev 22

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read_verilog -D TXUARTLITE -formal ../../rtl/rxuartlite.v
chparam -set CLOCKS_PER_BAUD 16
prep -top rxuartlite -nordff
clk2fflogic
opt -share_all
write_smt2 -wires rxuartlite.smt2

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