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[/] [wbuart32/] [trunk/] [bench/] [verilog/] [helloworld.v] - Rev 5
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//////////////////////////////////////////////////////////////////////////////// // // Filename: helloworld.v // // Project: wbuart32, a full featured UART with simulator // // Purpose: To create a *very* simple UART test program, which can be used // as the top level design file of any FPGA program. // // With some modifications (discussed below), this RTL should be able to // run as a top-level testing file, requiring only the UART and clock pin // to work. // // Creator: Dan Gisselquist, Ph.D. // Gisselquist Technology, LLC // //////////////////////////////////////////////////////////////////////////////// // // Copyright (C) 2015-2016, Gisselquist Technology, LLC // // This program is free software (firmware): you can redistribute it and/or // modify it under the terms of the GNU General Public License as published // by the Free Software Foundation, either version 3 of the License, or (at // your option) any later version. // // This program is distributed in the hope that it will be useful, but WITHOUT // ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License // for more details. // // You should have received a copy of the GNU General Public License along // with this program. (It's in the $(ROOT)/doc directory, run make with no // target there if the PDF file isn't present.) If not, see // <http://www.gnu.org/licenses/> for a copy. // // License: GPL, v3, as defined and found on www.gnu.org, // http://www.gnu.org/licenses/gpl.html // // //////////////////////////////////////////////////////////////////////////////// // // // Uncomment the next line if you want this program to work as a standalone // (not verilated) RTL "program" to test your UART. You'll also need to set // your setup condition properly, though. I recommend setting it to the // ratio of your onboard clock to your desired baud rate. For more information // about how to set this, please see the specification. // //`define OPT_STANDALONE // module helloworld(i_clk, `ifndef OPT_STANDALONE i_setup, `endif o_uart_tx); // input i_clk; output wire o_uart_tx; `ifndef OPT_STANDALONE input [29:0] i_setup; `endif // If i_setup isnt set up as an input parameter, it needs to be set. // We do so here, to a setting appropriate to create a 115200 Baud // comms system from a 100MHz clock. This also sets us to an 8-bit // data word, 1-stop bit, and no parity. `ifdef OPT_STANDALONE wire [29:0] i_setup; assign i_setup = 30'd868; // 115200 Baud, if clk @ 100MHz `endif reg pwr_reset; initial pwr_reset = 1'b1; always @(posedge i_clk) pwr_reset <= 1'b0; reg [7:0] message [0:15]; initial begin message[ 0] = "H"; message[ 1] = "e"; message[ 2] = "l"; message[ 3] = "l"; message[ 4] = "o"; message[ 5] = ","; message[ 6] = " "; message[ 7] = "W"; message[ 8] = "o"; message[ 9] = "r"; message[10] = "l"; message[11] = "d"; message[12] = "!"; message[13] = " "; message[14] = "\r"; message[15] = "\n"; end reg [27:0] counter; initial counter = 28'hffffff0; always @(posedge i_clk) counter <= counter + 1'b1; wire tx_break, tx_busy; reg tx_stb; reg [3:0] tx_index; reg [7:0] tx_data; assign tx_break = 1'b0; initial tx_index = 4'h0; always @(posedge i_clk) if ((tx_stb)&&(!tx_busy)) tx_index <= tx_index + 1'b1; always @(posedge i_clk) tx_data <= message[tx_index]; initial tx_stb = 1'b0; always @(posedge i_clk) if (&counter) tx_stb <= 1'b1; else if ((tx_stb)&&(!tx_busy)&&(tx_index==4'hf)) tx_stb <= 1'b0; txuart transmitter(i_clk, pwr_reset, i_setup, tx_break, tx_stb, tx_data, o_uart_tx, tx_busy); endmodule
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