URL
https://opencores.org/ocsvn/wbuart32/wbuart32/trunk
Subversion Repositories wbuart32
[/] [wbuart32/] [trunk/] [wbuart32.core] - Rev 14
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CAPI=1
[main]
description = A full featured UART with Simulator
simulators = verilator
[fileset rtl]
files =
rtl/rxuart.v
rtl/txuart.v
rtl/ufifo.v
rtl/wbuart.v
file_type = verilogSource
[verilator]
verilator_options =
tb_toplevel = bench/cpp/linetest.cpp
top_module = linetest
source_type = CPP
src_files = bench/cpp/linetest.cpp bench/cpp/uartsim.cpp
include_files = bench/cpp/uartsim.h
[fileset tb_files]
files = bench/verilog/linetest.v
usage = verilator
file_type = verilogSource
scope = private
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