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[/] [wdsp/] [trunk/] [rtl/] [verilog/] [minsoc/] [pll/] [pll1.ppf] - Rev 7
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<?xml version="1.0" encoding="UTF-8" ?><!DOCTYPE pinplan><pinplan intended_family="Cyclone II" variation_name="pll1" megafunction_name="ALTPLL" specifies="all_ports"><global><pin name="inclk0" direction="input" scope="external" source="clock" /><pin name="c0" direction="output" scope="external" source="clock" /><pin name="c1" direction="output" scope="external" source="clock" /></global></pinplan>