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https://opencores.org/ocsvn/wdsp/wdsp/trunk
Subversion Repositories wdsp
[/] [wdsp/] [trunk/] [rtl/] [verilog/] [minsoc/] [wb_conmax/] [tags/] [start/] [x] - Rev 7
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// Master 0 Interface
input [dw-1:0] m0_data_i;
output [dw-1:0] m0_data_o;
input [aw-1:0] m0_addr_i;
input [sw-1:0] m0_sel_i;
input m0_we_i;
input m0_cyc_i;
input m0_stb_i;
output m0_ack_o;
output m0_err_o;
output m0_rty_o;
// Master 1 Interface
input [dw-1:0] m1_data_i;
output [dw-1:0] m1_data_o;
input [aw-1:0] m1_addr_i;
input [sw-1:0] m1_sel_i;
input m1_we_i;
input m1_cyc_i;
input m1_stb_i;
output m1_ack_o;
output m1_err_o;
output m1_rty_o;
// Master 2 Interface
input [dw-1:0] m2_data_i;
output [dw-1:0] m2_data_o;
input [aw-1:0] m2_addr_i;
input [sw-1:0] m2_sel_i;
input m2_we_i;
input m2_cyc_i;
input m2_stb_i;
output m2_ack_o;
output m2_err_o;
output m2_rty_o;
// Master 3 Interface
input [dw-1:0] m3_data_i;
output [dw-1:0] m3_data_o;
input [aw-1:0] m3_addr_i;
input [sw-1:0] m3_sel_i;
input m3_we_i;
input m3_cyc_i;
input m3_stb_i;
output m3_ack_o;
output m3_err_o;
output m3_rty_o;
// Master 4 Interface
input [dw-1:0] m4_data_i;
output [dw-1:0] m4_data_o;
input [aw-1:0] m4_addr_i;
input [sw-1:0] m4_sel_i;
input m4_we_i;
input m4_cyc_i;
input m4_stb_i;
output m4_ack_o;
output m4_err_o;
output m4_rty_o;
// Master 5 Interface
input [dw-1:0] m5_data_i;
output [dw-1:0] m5_data_o;
input [aw-1:0] m5_addr_i;
input [sw-1:0] m5_sel_i;
input m5_we_i;
input m5_cyc_i;
input m5_stb_i;
output m5_ack_o;
output m5_err_o;
output m5_rty_o;
// Master 6 Interface
input [dw-1:0] m6_data_i;
output [dw-1:0] m6_data_o;
input [aw-1:0] m6_addr_i;
input [sw-1:0] m6_sel_i;
input m6_we_i;
input m6_cyc_i;
input m6_stb_i;
output m6_ack_o;
output m6_err_o;
output m6_rty_o;
// Master 7 Interface
input [dw-1:0] m7_data_i;
output [dw-1:0] m7_data_o;
input [aw-1:0] m7_addr_i;
input [sw-1:0] m7_sel_i;
input m7_we_i;
input m7_cyc_i;
input m7_stb_i;
output m7_ack_o;
output m7_err_o;
output m7_rty_o;
// Slave 0 Interface
input [dw-1:0] s0_data_i;
output [dw-1:0] s0_data_o;
output [aw-1:0] s0_addr_o;
output [sw-1:0] s0_sel_o;
output s0_we_o;
output s0_cyc_o;
output s0_stb_o;
input s0_ack_i;
input s0_err_i;
input s0_rty_i;
// Slave 1 Interface
input [dw-1:0] s1_data_i;
output [dw-1:0] s1_data_o;
output [aw-1:0] s1_addr_o;
output [sw-1:0] s1_sel_o;
output s1_we_o;
output s1_cyc_o;
output s1_stb_o;
input s1_ack_i;
input s1_err_i;
input s1_rty_i;
// Slave 2 Interface
input [dw-1:0] s2_data_i;
output [dw-1:0] s2_data_o;
output [aw-1:0] s2_addr_o;
output [sw-1:0] s2_sel_o;
output s2_we_o;
output s2_cyc_o;
output s2_stb_o;
input s2_ack_i;
input s2_err_i;
input s2_rty_i;
// Slave 3 Interface
input [dw-1:0] s3_data_i;
output [dw-1:0] s3_data_o;
output [aw-1:0] s3_addr_o;
output [sw-1:0] s3_sel_o;
output s3_we_o;
output s3_cyc_o;
output s3_stb_o;
input s3_ack_i;
input s3_err_i;
input s3_rty_i;
// Slave 4 Interface
input [dw-1:0] s4_data_i;
output [dw-1:0] s4_data_o;
output [aw-1:0] s4_addr_o;
output [sw-1:0] s4_sel_o;
output s4_we_o;
output s4_cyc_o;
output s4_stb_o;
input s4_ack_i;
input s4_err_i;
input s4_rty_i;
// Slave 5 Interface
input [dw-1:0] s5_data_i;
output [dw-1:0] s5_data_o;
output [aw-1:0] s5_addr_o;
output [sw-1:0] s5_sel_o;
output s5_we_o;
output s5_cyc_o;
output s5_stb_o;
input s5_ack_i;
input s5_err_i;
input s5_rty_i;
// Slave 6 Interface
input [dw-1:0] s6_data_i;
output [dw-1:0] s6_data_o;
output [aw-1:0] s6_addr_o;
output [sw-1:0] s6_sel_o;
output s6_we_o;
output s6_cyc_o;
output s6_stb_o;
input s6_ack_i;
input s6_err_i;
input s6_rty_i;
// Slave 7 Interface
input [dw-1:0] s7_data_i;
output [dw-1:0] s7_data_o;
output [aw-1:0] s7_addr_o;
output [sw-1:0] s7_sel_o;
output s7_we_o;
output s7_cyc_o;
output s7_stb_o;
input s7_ack_i;
input s7_err_i;
input s7_rty_i;
// Slave 8 Interface
input [dw-1:0] s8_data_i;
output [dw-1:0] s8_data_o;
output [aw-1:0] s8_addr_o;
output [sw-1:0] s8_sel_o;
output s8_we_o;
output s8_cyc_o;
output s8_stb_o;
input s8_ack_i;
input s8_err_i;
input s8_rty_i;
// Slave 9 Interface
input [dw-1:0] s9_data_i;
output [dw-1:0] s9_data_o;
output [aw-1:0] s9_addr_o;
output [sw-1:0] s9_sel_o;
output s9_we_o;
output s9_cyc_o;
output s9_stb_o;
input s9_ack_i;
input s9_err_i;
input s9_rty_i;
// Slave 10 Interface
input [dw-1:0] s10_data_i;
output [dw-1:0] s10_data_o;
output [aw-1:0] s10_addr_o;
output [sw-1:0] s10_sel_o;
output s10_we_o;
output s10_cyc_o;
output s10_stb_o;
input s10_ack_i;
input s10_err_i;
input s10_rty_i;
// Slave 11 Interface
input [dw-1:0] s11_data_i;
output [dw-1:0] s11_data_o;
output [aw-1:0] s11_addr_o;
output [sw-1:0] s11_sel_o;
output s11_we_o;
output s11_cyc_o;
output s11_stb_o;
input s11_ack_i;
input s11_err_i;
input s11_rty_i;
// Slave 12 Interface
input [dw-1:0] s12_data_i;
output [dw-1:0] s12_data_o;
output [aw-1:0] s12_addr_o;
output [sw-1:0] s12_sel_o;
output s12_we_o;
output s12_cyc_o;
output s12_stb_o;
input s12_ack_i;
input s12_err_i;
input s12_rty_i;
// Slave 13 Interface
input [dw-1:0] s13_data_i;
output [dw-1:0] s13_data_o;
output [aw-1:0] s13_addr_o;
output [sw-1:0] s13_sel_o;
output s13_we_o;
output s13_cyc_o;
output s13_stb_o;
input s13_ack_i;
input s13_err_i;
input s13_rty_i;
// Slave 14 Interface
input [dw-1:0] s14_data_i;
output [dw-1:0] s14_data_o;
output [aw-1:0] s14_addr_o;
output [sw-1:0] s14_sel_o;
output s14_we_o;
output s14_cyc_o;
output s14_stb_o;
input s14_ack_i;
input s14_err_i;
input s14_rty_i;
// Slave 15 Interface
input [dw-1:0] s15_data_i;
output [dw-1:0] s15_data_o;
output [aw-1:0] s15_addr_o;
output [sw-1:0] s15_sel_o;
output s15_we_o;
output s15_cyc_o;
output s15_stb_o;
input s15_ack_i;
input s15_err_i;
input s15_rty_i;