URL
https://opencores.org/ocsvn/wf3d/wf3d/trunk
Subversion Repositories wf3d
[/] [wf3d/] [trunk/] [implement/] [rtl/] [fm_hvc/] [fm_afifo.v] - Rev 2
Go to most recent revision | Compare with Previous | Blame | View Log
//======================================================================= // Project Monophony // Wire-Frame 3D Graphics Accelerator IP Core // // File: // fm_afifo.v // // Abstract: // Asynchronus FIFO // // Author: // Kenji Ishimaru (kenji.ishimaru@prtissimo.com) // //====================================================================== // // Copyright (c) 2015, Kenji Ishimaru // All rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: // // -Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. // -Redistributions in binary form must reproduce the above copyright notice, // this list of conditions and the following disclaimer in the documentation // and/or other materials provided with the distribution. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, // THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR // PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR // CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, // PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; // OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, // WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR // OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, // EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // // Revision History module fm_afifo ( clk_core, clk_vi, rst_x, i_color_mode, i_wstrobe, i_dt, o_full, i_renable, o_dt, o_empty, o_dnum ); // set default parameters parameter P_RANGE = 7; parameter P_DEPTH = 1 << P_RANGE; // 128 //////////////////////////// // I/O definition //////////////////////////// input clk_core; // system clock input clk_vi; input rst_x; // system reset input [1:0] i_color_mode; input i_wstrobe; // write strobe input [31:0] i_dt; // write data output o_full; // write data full input i_renable; // read enable output [15:0] o_dt; // read data output o_empty; // read data empty output [P_RANGE:0] o_dnum; // written data number ///////////////////////// // Register definition ///////////////////////// reg [P_RANGE-1:0] r_write_counter; reg [P_RANGE-1:0] r_read_counter; // data registers reg [2:0] r_select_hw; ///////////////////////// // wire definition ///////////////////////// wire o_full; wire o_empty; wire [15:0] o_dt; wire w_we; wire w_re; wire [31:0] w_dt32; wire [P_RANGE-1:0] w_read_counter_inc; wire [P_RANGE-1:0] w_read_counter; wire [15:0] w_dt16; wire [7:0] w_dt8; wire [3:0] w_dt4; // ///////////////////////// // assign statement ///////////////////////// assign w_dt16 = (r_select_hw[0]) ? w_dt32[31:16] : w_dt32[15:0]; assign w_dt8 = (r_select_hw[1:0] == 'd3) ? w_dt32[31:24] : (r_select_hw[1:0] == 'd2) ? w_dt32[23:16] : (r_select_hw[1:0] == 'd1) ? w_dt32[15:8] : w_dt32[7:0]; assign w_dt4 = (r_select_hw[2:0] == 'd7) ? w_dt32[31:28] : (r_select_hw[2:0] == 'd6) ? w_dt32[27:24] : (r_select_hw[2:0] == 'd5) ? w_dt32[23:20] : (r_select_hw[2:0] == 'd4) ? w_dt32[19:16] : (r_select_hw[2:0] == 'd3) ? w_dt32[15:12] : (r_select_hw[2:0] == 'd2) ? w_dt32[11:8] : (r_select_hw[2:0] == 'd1) ? w_dt32[7:4] : w_dt32[3:0]; assign o_dt = (i_color_mode == 'd3) ? {12'd0,w_dt4} : (i_color_mode == 'd2) ? {8'd0,w_dt8} : w_dt16 ; assign o_dnum = 0; assign o_full = 1'b0; assign o_empty = 1'b0; assign w_we = i_wstrobe; assign w_re = i_renable & ((i_color_mode == 'd3) ? (r_select_hw == 'd7) : (i_color_mode == 'd2) ? (r_select_hw[1:0] == 'd3) : (r_select_hw[0] == 'd1) ); assign w_read_counter_inc = r_read_counter + 1'b1; assign w_read_counter = (w_re) ? w_read_counter_inc : r_read_counter; //////////////////////// // always /////////////////////// // write side (clk_core) always @(posedge clk_core or negedge rst_x) begin if (~rst_x) begin r_write_counter <= 'd0; end else begin if (w_we) begin r_write_counter <= r_write_counter + 1'b1; end end end // read side (clk_vi) always @(posedge clk_vi or negedge rst_x) begin if (~rst_x) begin r_read_counter <= 'd0; end else begin if (w_re) begin r_read_counter <= w_read_counter_inc; end end end // select half word always @(posedge clk_vi or negedge rst_x) begin if (~rst_x) begin r_select_hw <= 3'b0; end else begin if (i_renable) r_select_hw <= r_select_hw + 1'b1; end end /////////////////// // module instance /////////////////// fm_cmn_ram #(.P_RAM_TYPE("TYPE_A"),.P_WIDTH(32),.P_RANGE( P_RANGE)) ram_00 ( .clka(clk_core), .clkb(clk_vi), .wea(w_we), .addra(r_write_counter), .addrb(w_read_counter), .dia(i_dt), .doa(), .dob(w_dt32) ); endmodule
Go to most recent revision | Compare with Previous | Blame | View Log