Subversion Repositories wf3d

# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
# Date created = 08:16:54  July 05, 2013
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#               usbhost_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#               assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
#    file is updated automatically by the Quartus II software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name DEVICE EP3C16F484C6
set_global_assignment -name TOP_LEVEL_ENTITY d3d_top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "08:16:54  JULY 05, 2013"
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
set_location_assignment PIN_G21 -to CLK
set_location_assignment PIN_B1 -to LEDG[9]
set_location_assignment PIN_B2 -to LEDG[8]
set_location_assignment PIN_C2 -to LEDG[7]
set_location_assignment PIN_C1 -to LEDG[6]
set_location_assignment PIN_E1 -to LEDG[5]
set_location_assignment PIN_F2 -to LEDG[4]
set_location_assignment PIN_H1 -to LEDG[3]
set_location_assignment PIN_J3 -to LEDG[2]
set_location_assignment PIN_J2 -to LEDG[1]
set_location_assignment PIN_J1 -to LEDG[0]
set_location_assignment PIN_E4 -to SW[8]
set_location_assignment PIN_E3 -to SW[7]
set_location_assignment PIN_H7 -to SW[6]
set_location_assignment PIN_J7 -to SW[5]
set_location_assignment PIN_G5 -to SW[4]
set_location_assignment PIN_G4 -to SW[3]
set_location_assignment PIN_H6 -to SW[2]
set_location_assignment PIN_H5 -to SW[1]
set_location_assignment PIN_J6 -to SW[0]
set_location_assignment PIN_F1 -to nBUTTON[2]
set_location_assignment PIN_G3 -to nBUTTON[1]
#set_location_assignment PIN_H2 -to nBUTTON[0]
set_location_assignment PIN_H2 -to RST
set_location_assignment PIN_U22 -to UART_RXD
set_location_assignment PIN_U21 -to UART_TXD
set_location_assignment PIN_V22 -to UART_RTS
set_location_assignment PIN_V21 -to UART_CTS
set_location_assignment PIN_J21 -to VGA_G[3]
set_location_assignment PIN_K17 -to VGA_G[2]
set_location_assignment PIN_J17 -to VGA_G[1]
set_location_assignment PIN_H22 -to VGA_G[0]
set_location_assignment PIN_L21 -to VGA_HS
set_location_assignment PIN_L22 -to VGA_VS
set_location_assignment PIN_H21 -to VGA_R[3]
set_location_assignment PIN_H20 -to VGA_R[2]
set_location_assignment PIN_H17 -to VGA_R[1]
set_location_assignment PIN_H19 -to VGA_R[0]
set_location_assignment PIN_K18 -to VGA_B[3]
set_location_assignment PIN_J22 -to VGA_B[2]
set_location_assignment PIN_K21 -to VGA_B[1]
set_location_assignment PIN_K22 -to VGA_B[0]
set_location_assignment PIN_E11 -to nHEX0[0]
set_location_assignment PIN_F11 -to nHEX0[1]
set_location_assignment PIN_H12 -to nHEX0[2]
set_location_assignment PIN_H13 -to nHEX0[3]
set_location_assignment PIN_G12 -to nHEX0[4]
set_location_assignment PIN_F12 -to nHEX0[5]
set_location_assignment PIN_F13 -to nHEX0[6]
set_location_assignment PIN_D13 -to nHEX0[7]
set_location_assignment PIN_A15 -to nHEX1[6]
set_location_assignment PIN_E14 -to nHEX1[5]
set_location_assignment PIN_B14 -to nHEX1[4]
set_location_assignment PIN_A14 -to nHEX1[3]
set_location_assignment PIN_C13 -to nHEX1[2]
set_location_assignment PIN_B13 -to nHEX1[1]
set_location_assignment PIN_A13 -to nHEX1[0]
set_location_assignment PIN_B15 -to nHEX1[7]
set_location_assignment PIN_F14 -to nHEX2[6]
set_location_assignment PIN_B17 -to nHEX2[5]
set_location_assignment PIN_A17 -to nHEX2[4]
set_location_assignment PIN_E15 -to nHEX2[3]
set_location_assignment PIN_B16 -to nHEX2[2]
set_location_assignment PIN_A16 -to nHEX2[1]
set_location_assignment PIN_D15 -to nHEX2[0]
set_location_assignment PIN_A18 -to nHEX2[7]
set_location_assignment PIN_G15 -to nHEX3[6]
set_location_assignment PIN_D19 -to nHEX3[5]
set_location_assignment PIN_C19 -to nHEX3[4]
set_location_assignment PIN_B19 -to nHEX3[3]
set_location_assignment PIN_A19 -to nHEX3[2]
set_location_assignment PIN_F15 -to nHEX3[1]
set_location_assignment PIN_B18 -to nHEX3[0]
set_location_assignment PIN_G16 -to nHEX3[7]
set_location_assignment PIN_G8 -to DRAM_CAS_N
set_location_assignment PIN_G7 -to DRAM_CS_N
set_location_assignment PIN_E5 -to DRAM_CLK
set_location_assignment PIN_E6 -to DRAM_CKE
set_location_assignment PIN_B5 -to DRAM_BA[0]
set_location_assignment PIN_A4 -to DRAM_BA[1]
set_location_assignment PIN_F10 -to DRAM_DQ[15]
set_location_assignment PIN_E10 -to DRAM_DQ[14]
set_location_assignment PIN_A10 -to DRAM_DQ[13]
set_location_assignment PIN_B10 -to DRAM_DQ[12]
set_location_assignment PIN_C10 -to DRAM_DQ[11]
set_location_assignment PIN_A9 -to DRAM_DQ[10]
set_location_assignment PIN_B9 -to DRAM_DQ[9]
set_location_assignment PIN_A8 -to DRAM_DQ[8]
set_location_assignment PIN_F8 -to DRAM_DQ[7]
set_location_assignment PIN_H9 -to DRAM_DQ[6]
set_location_assignment PIN_G9 -to DRAM_DQ[5]
set_location_assignment PIN_F9 -to DRAM_DQ[4]
set_location_assignment PIN_E9 -to DRAM_DQ[3]
set_location_assignment PIN_H10 -to DRAM_DQ[2]
set_location_assignment PIN_G10 -to DRAM_DQ[1]
set_location_assignment PIN_D10 -to DRAM_DQ[0]
set_location_assignment PIN_E7 -to DRAM_DQM[0]
set_location_assignment PIN_B8 -to DRAM_DQM[1]
set_location_assignment PIN_F7 -to DRAM_RAS_N
set_location_assignment PIN_D6 -to DRAM_WE_N
set_location_assignment PIN_C8 -to DRAM_ADDR[12]
set_location_assignment PIN_A7 -to DRAM_ADDR[11]
set_location_assignment PIN_B4 -to DRAM_ADDR[10]
set_location_assignment PIN_B7 -to DRAM_ADDR[9]
set_location_assignment PIN_C7 -to DRAM_ADDR[8]
set_location_assignment PIN_A6 -to DRAM_ADDR[7]
set_location_assignment PIN_B6 -to DRAM_ADDR[6]
set_location_assignment PIN_C6 -to DRAM_ADDR[5]
set_location_assignment PIN_A5 -to DRAM_ADDR[4]
set_location_assignment PIN_C3 -to DRAM_ADDR[3]
set_location_assignment PIN_B3 -to DRAM_ADDR[2]
set_location_assignment PIN_A3 -to DRAM_ADDR[1]
set_location_assignment PIN_C4 -to DRAM_ADDR[0]

set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_location_assignment PIN_U8 -to USB_DP
set_location_assignment PIN_Y7 -to USB_DN
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RST
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_DN
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDG[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to USB_DP
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION OFF
set_location_assignment PIN_K1 -to DATA
set_location_assignment PIN_K2 -to DCLK
set_location_assignment PIN_E2 -to SCE
set_location_assignment PIN_D1 -to SDO
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DATA
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DCLK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SCE
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDO
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE AUTO
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
set_global_assignment -name SEARCH_PATH ../../../../rtl/include

set_global_assignment -name VERILOG_FILE ../../../../rtl/core/fm_geo_tri.v
set_global_assignment -name VERILOG_FILE ../../../../rtl/core/fm_3d_f22_to_i.v
set_global_assignment -name VERILOG_FILE ../../../../rtl/core/fm_geo_clip.v
set_global_assignment -name VERILOG_FILE ../../../../rtl/core/fm_geo_cull.v
set_global_assignment -name VERILOG_FILE ../../../../rtl/core/fm_3d_norm.v
set_global_assignment -name VERILOG_FILE ../../../../rtl/core/fm_3d_fcnv.v
set_global_assignment -name VERILOG_FILE ../../../../rtl/core/fm_3d_frcp_rom.v
set_global_assignment -name VERILOG_FILE ../../../../rtl/core/fm_3d_frcp.v
set_global_assignment -name VERILOG_FILE ../../../../rtl/core/fm_3d_fmul.v
set_global_assignment -name VERILOG_FILE ../../../../rtl/core/fm_3d_fadd.v
set_global_assignment -name VERILOG_FILE ../../../../rtl/core/fm_sys.v
set_global_assignment -name VERILOG_FILE ../../../../rtl/core/fm_geo_viewport.v
set_global_assignment -name VERILOG_FILE ../../../../rtl/core/fm_ras_state.v
set_global_assignment -name VERILOG_FILE ../../../../rtl/core/fm_ras_mem.v
set_global_assignment -name VERILOG_FILE ../../../../rtl/core/fm_ras_line.v
set_global_assignment -name VERILOG_FILE ../../../../rtl/core/fm_ras.v
set_global_assignment -name VERILOG_FILE ../../../../rtl/core/fm_geo_persdiv.v
set_global_assignment -name VERILOG_FILE ../../../../rtl/core/fm_mem_arb.v
set_global_assignment -name VERILOG_FILE ../../../../rtl/core/fm_geo_matrix.v
set_global_assignment -name VERILOG_FILE ../../../../rtl/core/fm_geo_mem.v
set_global_assignment -name VERILOG_FILE ../../../../rtl/core/fm_geo.v
set_global_assignment -name VERILOG_FILE ../../../../rtl/core/fm_3d_core.v
set_global_assignment -name VERILOG_FILE ../../../rtl/fm_hvc/fm_cmn_ram.v
set_global_assignment -name VERILOG_FILE ../../../rtl/fm_hvc/fm_hvc_dma.v
set_global_assignment -name VERILOG_FILE ../../../rtl/fm_hvc/fm_hvc_data.v
set_global_assignment -name VERILOG_FILE ../../../rtl/fm_hvc/fm_hvc_core.v
set_global_assignment -name VERILOG_FILE ../../../rtl/fm_hvc/fm_hvc.v
set_global_assignment -name VERILOG_FILE ../../../rtl/fm_hvc/fm_afifo.v
set_global_assignment -name VERILOG_FILE ../../../rtl/de0/fm_hsys.v
set_global_assignment -name VERILOG_FILE ../../../rtl/de0/fm_avalon.v
set_global_assignment -name VERILOG_FILE ../../../rtl/de0/fm_avalon_wb.v
set_global_assignment -name QSYS_FILE d3d_system.qsys
set_global_assignment -name VERILOG_FILE ../../../rtl/de0/d3d_top.v
set_global_assignment -name SDC_FILE d3d.sdc
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA OFF
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top