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//////////////////////////////////////////////////////////////////////
//// ////
//// weigand_tx_top.v ////
//// ////
//// ////
//// This file is part of the Time Triggered Protocol Controller ////
//// http://www.opencores.org/projects/weigand/ ////
//// ////
//// ////
//// Author(s): ////
//// Jeff Anderson ////
//// jeaander@opencores.org ////
//// ////
//// ////
//// All additional information is available in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2013 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//// The Weigand protocol is maintained by ////
//// This product has been tested to interoperate with certified ////
//// devices, but has not been certified itself. This product ////
//// should be certified through prior to claiming strict ////
//// adherence to the standard. ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// Revisions at end of file
//
`include "timescale.v"
module testcase_1;
testbench_top testbench();
endmodule