Subversion Repositories wiegand_ctl

{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1424102406239 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 64-Bit " "Running Quartus II 64-Bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 14.0.0 Build 200 06/17/2014 SJ Web Edition " "Version 14.0.0 Build 200 06/17/2014 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1424102406239 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Feb 16 11:00:06 2015 " "Processing started: Mon Feb 16 11:00:06 2015" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1424102406239 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1424102406239 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off wiegand_tx_top -c wiegand_tx_top " "Command: quartus_eda --read_settings_files=off --write_settings_files=off wiegand_tx_top -c wiegand_tx_top" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1424102406239 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "wiegand_tx_top_6_1200mv_85c_slow.vo C:/Users/jeffA/Desktop/rtl/wiegand/trunk/syn/altera/wiegand_tx/simulation/modelsim/ simulation " "Generated file wiegand_tx_top_6_1200mv_85c_slow.vo in folder \"C:/Users/jeffA/Desktop/rtl/wiegand/trunk/syn/altera/wiegand_tx/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1424102406957 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "wiegand_tx_top_6_1200mv_0c_slow.vo C:/Users/jeffA/Desktop/rtl/wiegand/trunk/syn/altera/wiegand_tx/simulation/modelsim/ simulation " "Generated file wiegand_tx_top_6_1200mv_0c_slow.vo in folder \"C:/Users/jeffA/Desktop/rtl/wiegand/trunk/syn/altera/wiegand_tx/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1424102407191 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "wiegand_tx_top_min_1200mv_0c_fast.vo C:/Users/jeffA/Desktop/rtl/wiegand/trunk/syn/altera/wiegand_tx/simulation/modelsim/ simulation " "Generated file wiegand_tx_top_min_1200mv_0c_fast.vo in folder \"C:/Users/jeffA/Desktop/rtl/wiegand/trunk/syn/altera/wiegand_tx/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1424102407409 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "wiegand_tx_top.vo C:/Users/jeffA/Desktop/rtl/wiegand/trunk/syn/altera/wiegand_tx/simulation/modelsim/ simulation " "Generated file wiegand_tx_top.vo in folder \"C:/Users/jeffA/Desktop/rtl/wiegand/trunk/syn/altera/wiegand_tx/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1424102407597 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "wiegand_tx_top_6_1200mv_85c_v_slow.sdo C:/Users/jeffA/Desktop/rtl/wiegand/trunk/syn/altera/wiegand_tx/simulation/modelsim/ simulation " "Generated file wiegand_tx_top_6_1200mv_85c_v_slow.sdo in folder \"C:/Users/jeffA/Desktop/rtl/wiegand/trunk/syn/altera/wiegand_tx/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1424102407768 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "wiegand_tx_top_6_1200mv_0c_v_slow.sdo C:/Users/jeffA/Desktop/rtl/wiegand/trunk/syn/altera/wiegand_tx/simulation/modelsim/ simulation " "Generated file wiegand_tx_top_6_1200mv_0c_v_slow.sdo in folder \"C:/Users/jeffA/Desktop/rtl/wiegand/trunk/syn/altera/wiegand_tx/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1424102407955 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "wiegand_tx_top_min_1200mv_0c_v_fast.sdo C:/Users/jeffA/Desktop/rtl/wiegand/trunk/syn/altera/wiegand_tx/simulation/modelsim/ simulation " "Generated file wiegand_tx_top_min_1200mv_0c_v_fast.sdo in folder \"C:/Users/jeffA/Desktop/rtl/wiegand/trunk/syn/altera/wiegand_tx/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1424102408127 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "wiegand_tx_top_v.sdo C:/Users/jeffA/Desktop/rtl/wiegand/trunk/syn/altera/wiegand_tx/simulation/modelsim/ simulation " "Generated file wiegand_tx_top_v.sdo in folder \"C:/Users/jeffA/Desktop/rtl/wiegand/trunk/syn/altera/wiegand_tx/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1424102408252 ""}
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "511 " "Peak virtual memory: 511 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1424102408361 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Feb 16 11:00:08 2015 " "Processing ended: Mon Feb 16 11:00:08 2015" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1424102408361 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1424102408361 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1424102408361 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1424102408361 ""}