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[/] [wiegand_ctl/] [trunk/] [syn/] [altera/] [wiegand_tx/] [output_files/] [wiegand_tx_top.flow.rpt] - Rev 17
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Flow report for wiegand_tx_top
Mon Feb 16 11:00:08 2015
Quartus II 64-Bit Version 14.0.0 Build 200 06/17/2014 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Flow Summary
3. Flow Settings
4. Flow Non-Default Global Settings
5. Flow Elapsed Time
6. Flow OS Summary
7. Flow Log
8. Flow Messages
9. Flow Suppressed Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, the Altera Quartus II License Agreement,
the Altera MegaCore Function License Agreement, or other
applicable license agreement, including, without limitation,
that your use is for the sole purpose of programming logic
devices manufactured by Altera and sold by Altera or its
authorized distributors. Please refer to the applicable
agreement for further details.
+---------------------------------------------------------------------------------+
; Flow Summary ;
+------------------------------------+--------------------------------------------+
; Flow Status ; Successful - Mon Feb 16 11:00:08 2015 ;
; Quartus II 64-Bit Version ; 14.0.0 Build 200 06/17/2014 SJ Web Edition ;
; Revision Name ; wiegand_tx_top ;
; Top-level Entity Name ; wiegand_tx_top ;
; Family ; Cyclone IV GX ;
; Total logic elements ; 353 / 21,280 ( 2 % ) ;
; Total combinational functions ; 242 / 21,280 ( 1 % ) ;
; Dedicated logic registers ; 303 / 21,280 ( 1 % ) ;
; Total registers ; 303 ;
; Total pins ; 87 / 167 ( 52 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 / 774,144 ( 0 % ) ;
; Embedded Multiplier 9-bit elements ; 0 / 80 ( 0 % ) ;
; Total GXB Receiver Channel PCS ; 0 / 4 ( 0 % ) ;
; Total GXB Receiver Channel PMA ; 0 / 4 ( 0 % ) ;
; Total GXB Transmitter Channel PCS ; 0 / 4 ( 0 % ) ;
; Total GXB Transmitter Channel PMA ; 0 / 4 ( 0 % ) ;
; Total PLLs ; 0 / 4 ( 0 % ) ;
; Device ; EP4CGX22CF19C6 ;
; Timing Models ; Final ;
+------------------------------------+--------------------------------------------+
+-----------------------------------------+
; Flow Settings ;
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 02/16/2015 10:59:28 ;
; Main task ; Compilation ;
; Revision Name ; wiegand_tx_top ;
+-------------------+---------------------+
+---------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+-------------------------------------+--------------------------------+---------------+-------------+----------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------------+--------------------------------+---------------+-------------+----------------+
; COMPILER_SIGNATURE_ID ; 61959091049986.142410236807396 ; -- ; -- ; -- ;
; EDA_OUTPUT_DATA_FORMAT ; Verilog Hdl ; -- ; -- ; eda_simulation ;
; EDA_SIMULATION_TOOL ; ModelSim-Altera (Verilog) ; <None> ; -- ; -- ;
; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ;
; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING ; -- ; -- ; Top ;
; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ;
; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
+-------------------------------------+--------------------------------+---------------+-------------+----------------+
+-------------------------------------------------------------------------------------------------------------------------------+
; Flow Elapsed Time ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:03 ; 1.0 ; 571 MB ; 00:00:03 ;
; Fitter ; 00:00:17 ; 1.0 ; 850 MB ; 00:00:17 ;
; Assembler ; 00:00:03 ; 1.0 ; 536 MB ; 00:00:02 ;
; TimeQuest Timing Analyzer ; 00:00:05 ; 1.0 ; 540 MB ; 00:00:05 ;
; EDA Netlist Writer ; 00:00:02 ; 1.0 ; 499 MB ; 00:00:02 ;
; Total ; 00:00:30 ; -- ; -- ; 00:00:29 ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
+----------------------------------------------------------------------------------------+
; Flow OS Summary ;
+---------------------------+------------------+-----------+------------+----------------+
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
+---------------------------+------------------+-----------+------------+----------------+
; Analysis & Synthesis ; jeffA-PC ; Windows 7 ; 6.1 ; x86_64 ;
; Fitter ; jeffA-PC ; Windows 7 ; 6.1 ; x86_64 ;
; Assembler ; jeffA-PC ; Windows 7 ; 6.1 ; x86_64 ;
; TimeQuest Timing Analyzer ; jeffA-PC ; Windows 7 ; 6.1 ; x86_64 ;
; EDA Netlist Writer ; jeffA-PC ; Windows 7 ; 6.1 ; x86_64 ;
+---------------------------+------------------+-----------+------------+----------------+
------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off wiegand_tx_top -c wiegand_tx_top
quartus_fit --read_settings_files=off --write_settings_files=off wiegand_tx_top -c wiegand_tx_top
quartus_asm --read_settings_files=off --write_settings_files=off wiegand_tx_top -c wiegand_tx_top
quartus_sta wiegand_tx_top -c wiegand_tx_top
quartus_eda --read_settings_files=off --write_settings_files=off wiegand_tx_top -c wiegand_tx_top