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<tr class="memitem:gab81f7edf097fc4a885fd6134a288a817"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#gab81f7edf097fc4a885fd6134a288a817">XIIC_READ_OPERATION</a>   1</td></tr>
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<tr class="memitem:gaa0040c82cb3f8c0bbff61cbbad86e1ac"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#gaa0040c82cb3f8c0bbff61cbbad86e1ac">XIIC_MASTER_ROLE</a>   1</td></tr>
<tr class="separator:gaa0040c82cb3f8c0bbff61cbbad86e1ac"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gacdf6b790e752c7f789c81ee4721bafe8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#gacdf6b790e752c7f789c81ee4721bafe8">XIIC_STOP</a>   0x00</td></tr>
<tr class="separator:gacdf6b790e752c7f789c81ee4721bafe8"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gab28be58b11c65ecc54fc2f0c300412c1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#gab28be58b11c65ecc54fc2f0c300412c1">XIic_ReadReg</a>(BaseAddress, RegOffset)   XIic_In32((BaseAddress) + (RegOffset))</td></tr>
<tr class="separator:gab28be58b11c65ecc54fc2f0c300412c1"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga7a9318f43afc81c1dbd30a27587ba51d"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#ga7a9318f43afc81c1dbd30a27587ba51d">XIic_WriteReg</a>(BaseAddress, RegOffset, RegisterValue)   XIic_Out32((BaseAddress) + (RegOffset), (RegisterValue))</td></tr>
<tr class="separator:ga7a9318f43afc81c1dbd30a27587ba51d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga17d0df7020d5264d20bbc36d276e276e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#ga17d0df7020d5264d20bbc36d276e276e">XIic_IntrGlobalDisable</a>(BaseAddress)   <a class="el" href="group__iic__v3__1.html#ga7a9318f43afc81c1dbd30a27587ba51d">XIic_WriteReg</a>((BaseAddress), <a class="el" href="group__iic__v3__1.html#gaa27d0e422717f97fac36688f403d320a">XIIC_DGIER_OFFSET</a>, 0)</td></tr>
<tr class="separator:ga17d0df7020d5264d20bbc36d276e276e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga7071fcf4cf60d65fd862653fa34faa21"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#ga7071fcf4cf60d65fd862653fa34faa21">XIic_IntrGlobalEnable</a>(BaseAddress)</td></tr>
<tr class="separator:ga7071fcf4cf60d65fd862653fa34faa21"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaa839067df3b55f3181db24ebd8db3187"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#gaa839067df3b55f3181db24ebd8db3187">XIic_IsIntrGlobalEnabled</a>(BaseAddress)</td></tr>
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<tr class="memitem:ga3bc448908013aceb690c84fdbb7d66a8"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#ga3bc448908013aceb690c84fdbb7d66a8">XIic_WriteIisr</a>(BaseAddress, Status)   <a class="el" href="group__iic__v3__1.html#ga7a9318f43afc81c1dbd30a27587ba51d">XIic_WriteReg</a>((BaseAddress), <a class="el" href="group__iic__v3__1.html#gafe67d115440977750c9a7299eb499798">XIIC_IISR_OFFSET</a>, (Status))</td></tr>
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<tr class="memitem:gaf69a6487ad62b105aa3bb8d0e25b7fe7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#gaf69a6487ad62b105aa3bb8d0e25b7fe7">XIic_ReadIisr</a>(BaseAddress)   <a class="el" href="group__iic__v3__1.html#gab28be58b11c65ecc54fc2f0c300412c1">XIic_ReadReg</a>((BaseAddress), <a class="el" href="group__iic__v3__1.html#gafe67d115440977750c9a7299eb499798">XIIC_IISR_OFFSET</a>)</td></tr>
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<tr class="memitem:ga2f926a076e9a6b80bea46664d2e55ee9"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#ga2f926a076e9a6b80bea46664d2e55ee9">XIic_WriteIier</a>(BaseAddress, Enable)   <a class="el" href="group__iic__v3__1.html#ga7a9318f43afc81c1dbd30a27587ba51d">XIic_WriteReg</a>((BaseAddress), <a class="el" href="group__iic__v3__1.html#ga6a6353babc7347287755655c810a1758">XIIC_IIER_OFFSET</a>, (Enable))</td></tr>
<tr class="separator:ga2f926a076e9a6b80bea46664d2e55ee9"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaee17ffc86a8270abeb1319e8c67ccce5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#gaee17ffc86a8270abeb1319e8c67ccce5">XIic_ReadIier</a>(BaseAddress)   <a class="el" href="group__iic__v3__1.html#gab28be58b11c65ecc54fc2f0c300412c1">XIic_ReadReg</a>((BaseAddress), <a class="el" href="group__iic__v3__1.html#ga6a6353babc7347287755655c810a1758">XIIC_IIER_OFFSET</a>)</td></tr>
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<tr class="memitem:gaf8fa6ffa77af5942fa1dbd1b5a666d55"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#gaf8fa6ffa77af5942fa1dbd1b5a666d55">XIic_ClearIisr</a>(BaseAddress, InterruptMask)</td></tr>
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<tr class="memitem:ga89d095e79795958bcbc15238a7bbfa32"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#ga89d095e79795958bcbc15238a7bbfa32">XIic_Send7BitAddress</a>(BaseAddress, SlaveAddress, Operation)</td></tr>
<tr class="separator:ga89d095e79795958bcbc15238a7bbfa32"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga81d32f9fd29736e9f9c7ef345527386b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#ga81d32f9fd29736e9f9c7ef345527386b">XIic_DynSend7BitAddress</a>(BaseAddress, SlaveAddress, Operation)</td></tr>
<tr class="separator:ga81d32f9fd29736e9f9c7ef345527386b"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga682d21ed5020daa5b5a863bbffb35cc5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#ga682d21ed5020daa5b5a863bbffb35cc5">XIic_DynSendStartStopAddress</a>(BaseAddress, SlaveAddress, Operation)</td></tr>
<tr class="separator:ga682d21ed5020daa5b5a863bbffb35cc5"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga22446f72b705b950e4b485ab9cdd2ae6"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#ga22446f72b705b950e4b485ab9cdd2ae6">XIic_DynSendStop</a>(BaseAddress, ByteCount)</td></tr>
<tr class="separator:ga22446f72b705b950e4b485ab9cdd2ae6"><td class="memSeparator" colspan="2"> </td></tr>
<tr><td colspan="2"><div class="groupHeader">Register Map</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Register offsets for the <a class="el" href="struct_x_iic.html" title="The XIic driver instance data. ">XIic</a> device. </p>
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<tr><td colspan="2"><div class="groupHeader">Device Global Interrupt Enable Register masks (CR) mask(s)</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">IIC Device Interrupt Status/Enable (INTR) Register Masks</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p><b> Interrupt Status Register (IISR) </b></p>
<p>This register holds the interrupt status flags for the Spi device.</p>
<p><b> Interrupt Enable Register (IIER) </b></p>
<p>This register is used to enable interrupt sources for the IIC device. Writing a '1' to a bit in this register enables the corresponding Interrupt. Writing a '0' to a bit in this register disables the corresponding Interrupt.</p>
<p>IISR/IIER registers have the same bit definitions and are only defined once. </p>
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<tr><td colspan="2"><div class="groupHeader">Reset Register mask</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Control Register masks (CR) mask(s)</div></td></tr>
<tr class="memitem:gaefca9cb59ce820ea4fbb4c35f5a1fa55"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#gaefca9cb59ce820ea4fbb4c35f5a1fa55">XIIC_CR_DIR_IS_TX_MASK</a>   0x00000008</td></tr>
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<tr class="memitem:ga79990adaa6f077302644d7b787b19c53"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#ga79990adaa6f077302644d7b787b19c53">XIIC_CR_NO_ACK_MASK</a>   0x00000010</td></tr>
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<tr><td colspan="2"><div class="groupHeader">Status Register masks (SR) mask(s)</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Data Tx Register (DTR) mask(s)</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Data Rx Register (DRR) mask(s)</div></td></tr>
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Functions</h2></td></tr>
<tr class="memitem:ga7a848238d75ff57837afa5a58f11f326"><td class="memItemLeft" align="right" valign="top">unsigned </td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#ga7a848238d75ff57837afa5a58f11f326">XIic_Recv</a> (UINTPTR BaseAddress, u8 Address, u8 *BufferPtr, unsigned ByteCount, u8 Option)</td></tr>
<tr class="separator:ga7a848238d75ff57837afa5a58f11f326"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga907c577b53407fb0bfc98d0ca37ee221"><td class="memItemLeft" align="right" valign="top">unsigned </td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#ga907c577b53407fb0bfc98d0ca37ee221">XIic_Send</a> (UINTPTR BaseAddress, u8 Address, u8 *BufferPtr, unsigned ByteCount, u8 Option)</td></tr>
<tr class="separator:ga907c577b53407fb0bfc98d0ca37ee221"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga9979fbd483e1c8c495c9eb2bfd7ad6e9"><td class="memItemLeft" align="right" valign="top">unsigned </td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#ga9979fbd483e1c8c495c9eb2bfd7ad6e9">XIic_DynRecv</a> (UINTPTR BaseAddress, u8 Address, u8 *BufferPtr, u8 ByteCount)</td></tr>
<tr class="separator:ga9979fbd483e1c8c495c9eb2bfd7ad6e9"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gadeaf11cda2466ae1c6036a3de0f52874"><td class="memItemLeft" align="right" valign="top">unsigned </td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#gadeaf11cda2466ae1c6036a3de0f52874">XIic_DynSend</a> (UINTPTR BaseAddress, u16 Address, u8 *BufferPtr, u8 ByteCount, u8 Option)</td></tr>
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<tr class="memitem:ga90f3806cf4817250596f6f68f2c066a3"><td class="memItemLeft" align="right" valign="top">u32 </td><td class="memItemRight" valign="bottom"><a class="el" href="group__iic__v3__1.html#ga90f3806cf4817250596f6f68f2c066a3">XIic_WaitBusFree</a> (UINTPTR BaseAddress)</td></tr>
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