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// IP VLNV: xilinx.com:ip:rxaui:4.3
// IP Revision: 7

// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.

//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
rxaui_0 your_instance_name (
  .reset(reset),                          // input wire reset
  .dclk(dclk),                            // input wire dclk
  .clk156_out(clk156_out),                // output wire clk156_out
  .clk156_lock(clk156_lock),              // output wire clk156_lock
  .refclk_out(refclk_out),                // output wire refclk_out
  .refclk_p(refclk_p),                    // input wire refclk_p
  .refclk_n(refclk_n),                    // input wire refclk_n
  .qplloutclk_out(qplloutclk_out),        // output wire qplloutclk_out
  .qplllock_out(qplllock_out),            // output wire qplllock_out
  .qplloutrefclk_out(qplloutrefclk_out),  // output wire qplloutrefclk_out
  .xgmii_txd(xgmii_txd),                  // input wire [63 : 0] xgmii_txd
  .xgmii_txc(xgmii_txc),                  // input wire [7 : 0] xgmii_txc
  .xgmii_rxd(xgmii_rxd),                  // output wire [63 : 0] xgmii_rxd
  .xgmii_rxc(xgmii_rxc),                  // output wire [7 : 0] xgmii_rxc
  .rxaui_tx_l0_p(rxaui_tx_l0_p),          // output wire rxaui_tx_l0_p
  .rxaui_tx_l0_n(rxaui_tx_l0_n),          // output wire rxaui_tx_l0_n
  .rxaui_tx_l1_p(rxaui_tx_l1_p),          // output wire rxaui_tx_l1_p
  .rxaui_tx_l1_n(rxaui_tx_l1_n),          // output wire rxaui_tx_l1_n
  .rxaui_rx_l0_p(rxaui_rx_l0_p),          // input wire rxaui_rx_l0_p
  .rxaui_rx_l0_n(rxaui_rx_l0_n),          // input wire rxaui_rx_l0_n
  .rxaui_rx_l1_p(rxaui_rx_l1_p),          // input wire rxaui_rx_l1_p
  .rxaui_rx_l1_n(rxaui_rx_l1_n),          // input wire rxaui_rx_l1_n
  .signal_detect(signal_detect),          // input wire [1 : 0] signal_detect
  .debug(debug),                          // output wire [5 : 0] debug
  .mdc(mdc),                              // input wire mdc
  .mdio_in(mdio_in),                      // input wire mdio_in
  .mdio_out(mdio_out),                    // output wire mdio_out
  .mdio_tri(mdio_tri),                    // output wire mdio_tri
  .prtad(prtad),                          // input wire [4 : 0] prtad
  .type_sel(type_sel)                    // input wire [1 : 0] type_sel
);
// INST_TAG_END ------ End INSTANTIATION Template ---------

// You must compile the wrapper file rxaui_0.v when simulating
// the core, rxaui_0. When compiling the wrapper file, be sure to
// reference the Verilog simulation library.