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-- DO NOT MODIFY THIS FILE.

-- IP VLNV: xilinx.com:ip:rxaui:4.3
-- IP Revision: 7

-- The following code must appear in the VHDL architecture header.

------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
COMPONENT rxaui_0
  PORT (
    reset : IN STD_LOGIC;
    dclk : IN STD_LOGIC;
    clk156_out : OUT STD_LOGIC;
    clk156_lock : OUT STD_LOGIC;
    refclk_out : OUT STD_LOGIC;
    refclk_p : IN STD_LOGIC;
    refclk_n : IN STD_LOGIC;
    qplloutclk_out : OUT STD_LOGIC;
    qplllock_out : OUT STD_LOGIC;
    qplloutrefclk_out : OUT STD_LOGIC;
    xgmii_txd : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
    xgmii_txc : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
    xgmii_rxd : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
    xgmii_rxc : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
    rxaui_tx_l0_p : OUT STD_LOGIC;
    rxaui_tx_l0_n : OUT STD_LOGIC;
    rxaui_tx_l1_p : OUT STD_LOGIC;
    rxaui_tx_l1_n : OUT STD_LOGIC;
    rxaui_rx_l0_p : IN STD_LOGIC;
    rxaui_rx_l0_n : IN STD_LOGIC;
    rxaui_rx_l1_p : IN STD_LOGIC;
    rxaui_rx_l1_n : IN STD_LOGIC;
    signal_detect : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
    debug : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
    mdc : IN STD_LOGIC;
    mdio_in : IN STD_LOGIC;
    mdio_out : OUT STD_LOGIC;
    mdio_tri : OUT STD_LOGIC;
    prtad : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
    type_sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0)
  );
END COMPONENT;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------

-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.

------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : rxaui_0
  PORT MAP (
    reset => reset,
    dclk => dclk,
    clk156_out => clk156_out,
    clk156_lock => clk156_lock,
    refclk_out => refclk_out,
    refclk_p => refclk_p,
    refclk_n => refclk_n,
    qplloutclk_out => qplloutclk_out,
    qplllock_out => qplllock_out,
    qplloutrefclk_out => qplloutrefclk_out,
    xgmii_txd => xgmii_txd,
    xgmii_txc => xgmii_txc,
    xgmii_rxd => xgmii_rxd,
    xgmii_rxc => xgmii_rxc,
    rxaui_tx_l0_p => rxaui_tx_l0_p,
    rxaui_tx_l0_n => rxaui_tx_l0_n,
    rxaui_tx_l1_p => rxaui_tx_l1_p,
    rxaui_tx_l1_n => rxaui_tx_l1_n,
    rxaui_rx_l0_p => rxaui_rx_l0_p,
    rxaui_rx_l0_n => rxaui_rx_l0_n,
    rxaui_rx_l1_p => rxaui_rx_l1_p,
    rxaui_rx_l1_n => rxaui_rx_l1_n,
    signal_detect => signal_detect,
    debug => debug,
    mdc => mdc,
    mdio_in => mdio_in,
    mdio_out => mdio_out,
    mdio_tri => mdio_tri,
    prtad => prtad,
    type_sel => type_sel
  );
-- INST_TAG_END ------ End INSTANTIATION Template ---------

-- You must compile the wrapper file rxaui_0.vhd when simulating
-- the core, rxaui_0. When compiling the wrapper file, be sure to
-- reference the VHDL simulation library.