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<?xml version="1.0" encoding="UTF-8"?>
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>xilinx.com</spirit:vendor>
<spirit:library>customized_ip</spirit:library>
<spirit:name>rxaui_0</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
<spirit:name>mdio_interface</spirit:name>
<spirit:displayName>mdio_interface</spirit:displayName>
<spirit:description>mdio interface</spirit:description>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="mdio" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="mdio_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>MDC</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>mdc</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>MDIO_I</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>mdio_in</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>MDIO_O</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>mdio_out</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>MDIO_T</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>mdio_tri</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:vendorExtensions>
<xilinx:busInterfaceInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.mdio_interface" xilinx:dependency="spirit:decode(id('PARAM_VALUE.Mdio_Management')) = 1">true</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:busInterfaceInfo>
</spirit:vendorExtensions>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>xgmii_interface</spirit:name>
<spirit:displayName>xgmii_interface</spirit:displayName>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="xgmii" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="xgmii_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RXC</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>xgmii_rxc</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RXD</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>xgmii_rxd</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>TXC</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>xgmii_txc</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>TXD</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>xgmii_txd</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>gt0_drp</spirit:name>
<spirit:displayName>gt0_drp</spirit:displayName>
<spirit:description>DRP Interface to Transceiver 0</spirit:description>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="drp" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="drp_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>DADDR</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>gt0_drpaddr</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>DEN</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>gt0_drpen</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>DI</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>gt0_drpdi</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>DO</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>gt0_drpdo</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>DRDY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>gt0_drprdy</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>DWE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>gt0_drpwe</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:vendorExtensions>
<xilinx:busInterfaceInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.gt0_drp" xilinx:dependency="spirit:decode(id('PARAM_VALUE.TransceiverControl') and ((starts_with(id('PARAM_VALUE.Transceiver'),'GTHE3')) or (starts_with(id('PARAM_VALUE.Transceiver'),'GTYE3')) or (starts_with(id('PARAM_VALUE.Transceiver'),'GTHE4')) or (starts_with(id('PARAM_VALUE.Transceiver'),'GTYE4'))))">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:busInterfaceInfo>
</spirit:vendorExtensions>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>gt1_drp</spirit:name>
<spirit:displayName>gt1_drp</spirit:displayName>
<spirit:description>DRP Interface to Transceiver 1</spirit:description>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="drp" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="drp_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>DADDR</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>gt1_drpaddr</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>DEN</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>gt1_drpen</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>DI</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>gt1_drpdi</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>DO</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>gt1_drpdo</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>DRDY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>gt1_drprdy</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>DWE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>gt1_drpwe</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:vendorExtensions>
<xilinx:busInterfaceInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.gt1_drp" xilinx:dependency="spirit:decode(id('PARAM_VALUE.TransceiverControl') and ((starts_with(id('PARAM_VALUE.Transceiver'),'GTHE3')) or (starts_with(id('PARAM_VALUE.Transceiver'),'GTYE3')) or (starts_with(id('PARAM_VALUE.Transceiver'),'GTHE4')) or (starts_with(id('PARAM_VALUE.Transceiver'),'GTYE4'))))">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:busInterfaceInfo>
</spirit:vendorExtensions>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>drp0</spirit:name>
<spirit:displayName>drp0</spirit:displayName>
<spirit:description>DRP Interface to Transceiver 0</spirit:description>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="drp" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="drp_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>DADDR</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>gt0_drpaddr</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>DEN</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>gt0_drpen</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>DI</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>gt0_drpdi</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>DO</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>gt0_drpdo</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>DRDY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>gt0_drprdy</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>DWE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>gt0_drpwe</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:vendorExtensions>
<xilinx:busInterfaceInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.drp0" xilinx:dependency="spirit:decode(id('PARAM_VALUE.TransceiverControl') and ((starts_with(id('PARAM_VALUE.Transceiver'),'GTXE2')) or (starts_with(id('PARAM_VALUE.Transceiver'),'GTHE2')) or (starts_with(id('PARAM_VALUE.Transceiver'),'GTPE2'))))">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:busInterfaceInfo>
</spirit:vendorExtensions>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>drp1</spirit:name>
<spirit:displayName>drp1</spirit:displayName>
<spirit:description>DRP Interface to Transceiver 1</spirit:description>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="drp" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="drp_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>DADDR</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>gt1_drpaddr</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>DEN</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>gt1_drpen</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>DI</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>gt1_drpdi</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>DO</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>gt1_drpdo</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>DRDY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>gt1_drprdy</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>DWE</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>gt1_drpwe</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:vendorExtensions>
<xilinx:busInterfaceInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.drp1" xilinx:dependency="spirit:decode(id('PARAM_VALUE.TransceiverControl') and ((starts_with(id('PARAM_VALUE.Transceiver'),'GTXE2')) or (starts_with(id('PARAM_VALUE.Transceiver'),'GTHE2')) or (starts_with(id('PARAM_VALUE.Transceiver'),'GTPE2'))))">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:busInterfaceInfo>
</spirit:vendorExtensions>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>dclk_port</spirit:name>
<spirit:displayName>dclk</spirit:displayName>
<spirit:description>DRP Clock - free running clock used to clock DRP and some logic.</spirit:description>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CLK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>dclk</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.DCLK_PORT.ASSOCIATED_BUSIF">drp0:drp1</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>refclk_diff_port</spirit:name>
<spirit:displayName>refclk</spirit:displayName>
<spirit:description>Differential GT reference clock</spirit:description>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="diff_clock" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="diff_clock_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CLK_N</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>refclk_n</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CLK_P</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>refclk_p</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:vendorExtensions>
<xilinx:busInterfaceInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.refclk_diff_port" xilinx:dependency="id('PARAM_VALUE.SupportLevel') = '1'">true</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:busInterfaceInfo>
</spirit:vendorExtensions>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>refclk_port</spirit:name>
<spirit:displayName>refclk</spirit:displayName>
<spirit:description>GT reference clock</spirit:description>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CLK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>refclk</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:vendorExtensions>
<xilinx:busInterfaceInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.refclk_port" xilinx:dependency="(((starts_with(id('PARAM_VALUE.Transceiver'),'GTXE2')) or (starts_with(id('PARAM_VALUE.Transceiver'),'GTHE2')) or (starts_with(id('PARAM_VALUE.Transceiver'),'GTHE3')) or (starts_with(id('PARAM_VALUE.Transceiver'),'GTYE3')) or (starts_with(id('PARAM_VALUE.Transceiver'),'GTHE4')) or (starts_with(id('PARAM_VALUE.Transceiver'),'GTYE4'))) and (id('PARAM_VALUE.SupportLevel') = '0'))">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:busInterfaceInfo>
</spirit:vendorExtensions>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>refclk_out_port</spirit:name>
<spirit:displayName>refclk_out</spirit:displayName>
<spirit:description>Reference clock output from the differential transceiver clock buffer.</spirit:description>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
<spirit:master/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CLK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>refclk_out</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.REFCLK_OUT_PORT.FREQ_HZ">156250000</spirit:value>
</spirit:parameter>
</spirit:parameters>
<spirit:vendorExtensions>
<xilinx:busInterfaceInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.refclk_out_port" xilinx:dependency="(((starts_with(id('PARAM_VALUE.Transceiver'),'GTXE2')) or (starts_with(id('PARAM_VALUE.Transceiver'),'GTHE2')) or (starts_with(id('PARAM_VALUE.Transceiver'),'GTHE3')) or (starts_with(id('PARAM_VALUE.Transceiver'),'GTYE3')) or (starts_with(id('PARAM_VALUE.Transceiver'),'GTHE4')) or (starts_with(id('PARAM_VALUE.Transceiver'),'GTYE4'))) and (id('PARAM_VALUE.SupportLevel') = '1'))">true</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:busInterfaceInfo>
</spirit:vendorExtensions>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>clk156_out_port</spirit:name>
<spirit:displayName>clk156_out</spirit:displayName>
<spirit:description>156.25MHz output clock. Can be used to drive logic, but not another RXAUI instance.</spirit:description>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
<spirit:master/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CLK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>clk156_out</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLK156_OUT_PORT.ASSOCIATED_BUSIF">xgmii_interface</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>FREQ_HZ</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLK156_OUT_PORT.FREQ_HZ">156250000</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>qpll0outclk_out_port</spirit:name>
<spirit:displayName>qpll0outclk_out</spirit:displayName>
<spirit:description>Output from the quad PLL port QPLL0OUTCLK.</spirit:description>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
<spirit:master/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CLK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>qpll0outclk_out</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:vendorExtensions>
<xilinx:busInterfaceInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.qpll0outclk_out_port" xilinx:dependency="(((starts_with(id('PARAM_VALUE.Transceiver'),'GTHE3')) or (starts_with(id('PARAM_VALUE.Transceiver'),'GTYE3')) or (starts_with(id('PARAM_VALUE.Transceiver'),'GTHE4')) or (starts_with(id('PARAM_VALUE.Transceiver'),'GTYE4'))) and (id('PARAM_VALUE.SupportLevel') = '1'))">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:busInterfaceInfo>
</spirit:vendorExtensions>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>qpll0outrefclk_out_port</spirit:name>
<spirit:displayName>qpll0outrefclk_out</spirit:displayName>
<spirit:description>Output from the quad PLL port QPLL0OUTREFCLK.</spirit:description>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
<spirit:master/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CLK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>qpll0outrefclk_out</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:vendorExtensions>
<xilinx:busInterfaceInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.qpll0outrefclk_out_port" xilinx:dependency="(((starts_with(id('PARAM_VALUE.Transceiver'),'GTHE3')) or (starts_with(id('PARAM_VALUE.Transceiver'),'GTYE3')) or (starts_with(id('PARAM_VALUE.Transceiver'),'GTYE4'))) and (id('PARAM_VALUE.SupportLevel') = '1'))">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:busInterfaceInfo>
</spirit:vendorExtensions>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>qpll0outclk_port</spirit:name>
<spirit:displayName>qpll0outclk</spirit:displayName>
<spirit:description>Connect to the quad PLL output clock QPLL0OUTCLK.</spirit:description>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CLK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>qpll0outclk</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:vendorExtensions>
<xilinx:busInterfaceInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.qpll0outclk_port" xilinx:dependency="(((starts_with(id('PARAM_VALUE.Transceiver'),'GTHE3')) or (starts_with(id('PARAM_VALUE.Transceiver'),'GTYE3')) or (starts_with(id('PARAM_VALUE.Transceiver'),'GTHE4') or (starts_with(id('PARAM_VALUE.Transceiver'),'GTYE4')))) and (id('PARAM_VALUE.SupportLevel') = '0'))">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:busInterfaceInfo>
</spirit:vendorExtensions>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>qpll0outrefclk_port</spirit:name>
<spirit:displayName>qpll0outrefclk</spirit:displayName>
<spirit:description>Connect to the quad PLL output reference clock QPLL0OUTREFCLK.</spirit:description>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CLK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>qpll0outrefclk</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:vendorExtensions>
<xilinx:busInterfaceInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.qpll0outrefclk_port" xilinx:dependency="(((starts_with(id('PARAM_VALUE.Transceiver'),'GTHE3')) or (starts_with(id('PARAM_VALUE.Transceiver'),'GTYE3')) or (starts_with(id('PARAM_VALUE.Transceiver'),'GTHE4')) or (starts_with(id('PARAM_VALUE.Transceiver'),'GTYE4'))) and (id('PARAM_VALUE.SupportLevel') = '0'))">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:busInterfaceInfo>
</spirit:vendorExtensions>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>qplloutclk_out_port</spirit:name>
<spirit:displayName>qplloutclk_out</spirit:displayName>
<spirit:description>Output from the quad PLL port QPLLOUTCLK.</spirit:description>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
<spirit:master/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CLK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>qplloutclk_out</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:vendorExtensions>
<xilinx:busInterfaceInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.qplloutclk_out_port" xilinx:dependency="(((starts_with(id('PARAM_VALUE.Transceiver'),'GTXE2')) or (starts_with(id('PARAM_VALUE.Transceiver'),'GTHE2'))) and (id('PARAM_VALUE.SupportLevel') = '1'))">true</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:busInterfaceInfo>
</spirit:vendorExtensions>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>qplloutclk_port</spirit:name>
<spirit:displayName>qplloutclk</spirit:displayName>
<spirit:description>Connect to the quad PLL output clock QPLLOUTCLK.</spirit:description>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CLK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>qplloutclk</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:vendorExtensions>
<xilinx:busInterfaceInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.qplloutclk_port" xilinx:dependency="(((starts_with(id('PARAM_VALUE.Transceiver'),'GTXE2')) or (starts_with(id('PARAM_VALUE.Transceiver'),'GTHE2'))) and (id('PARAM_VALUE.SupportLevel') = '0'))">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:busInterfaceInfo>
</spirit:vendorExtensions>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>qplloutrefclk_out_port</spirit:name>
<spirit:displayName>qplloutrefclk_out</spirit:displayName>
<spirit:description>Output from the quad PLL port QPLLREFCLK.</spirit:description>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
<spirit:master/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CLK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>qplloutrefclk_out</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:vendorExtensions>
<xilinx:busInterfaceInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.qplloutrefclk_out_port" xilinx:dependency="(((starts_with(id('PARAM_VALUE.Transceiver'),'GTXE2')) or (starts_with(id('PARAM_VALUE.Transceiver'),'GTHE2'))) and (id('PARAM_VALUE.SupportLevel') = '1'))">true</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:busInterfaceInfo>
</spirit:vendorExtensions>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>qplloutrefclk_port</spirit:name>
<spirit:displayName>qplloutrefclk</spirit:displayName>
<spirit:description>Connect to the quad PLL output reference clock QPLLOUTREFCLK.</spirit:description>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CLK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>qplloutrefclk</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:vendorExtensions>
<xilinx:busInterfaceInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.qplloutrefclk_port" xilinx:dependency="(((starts_with(id('PARAM_VALUE.Transceiver'),'GTXE2')) or (starts_with(id('PARAM_VALUE.Transceiver'),'GTHE2'))) and (id('PARAM_VALUE.SupportLevel') = '0'))">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:busInterfaceInfo>
</spirit:vendorExtensions>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>pll0outclk_out_port</spirit:name>
<spirit:displayName>pll0outclk_out</spirit:displayName>
<spirit:description>Output from the GTPE2_COMMON PLL port PLL0OUTCLK.</spirit:description>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
<spirit:master/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CLK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>pll0outclk_out</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:vendorExtensions>
<xilinx:busInterfaceInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pll0outclk_out_port" xilinx:dependency="(starts_with(id('PARAM_VALUE.Transceiver'),'GTPE2') and (id('PARAM_VALUE.SupportLevel') = '1'))">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:busInterfaceInfo>
</spirit:vendorExtensions>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>pll0outclk_port</spirit:name>
<spirit:displayName>pll0outclk</spirit:displayName>
<spirit:description>Connect to the GTPE2_COMMON PLL port PLL0OUTCLK.</spirit:description>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CLK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>pll0outclk</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:vendorExtensions>
<xilinx:busInterfaceInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pll0outclk_port" xilinx:dependency="(starts_with(id('PARAM_VALUE.Transceiver'),'GTPE2') and (id('PARAM_VALUE.SupportLevel') = '0'))">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:busInterfaceInfo>
</spirit:vendorExtensions>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>pll0outrefclk_out_port</spirit:name>
<spirit:displayName>pll0outrefclk_out</spirit:displayName>
<spirit:description>Output from the GTPE2_COMMON PLL port PLL0OUTREFCLK</spirit:description>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
<spirit:master/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CLK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>pll0outrefclk_out</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:vendorExtensions>
<xilinx:busInterfaceInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pll0outrefclk_out_port" xilinx:dependency="(starts_with(id('PARAM_VALUE.Transceiver'),'GTPE2') and (id('PARAM_VALUE.SupportLevel') = '1'))">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:busInterfaceInfo>
</spirit:vendorExtensions>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>pll0outrefclk_port</spirit:name>
<spirit:displayName>pll0outrefclk</spirit:displayName>
<spirit:description>Connect to the GTPE2_COMMON PLL REFCLK port PLL0OUTREFCLK</spirit:description>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CLK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>pll0outrefclk</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:vendorExtensions>
<xilinx:busInterfaceInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pll0outrefclk_port" xilinx:dependency="(starts_with(id('PARAM_VALUE.Transceiver'),'GTPE2') and (id('PARAM_VALUE.SupportLevel') = '0'))">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:busInterfaceInfo>
</spirit:vendorExtensions>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>pll1outclk_out_out_port</spirit:name>
<spirit:displayName>pll1outclk_out</spirit:displayName>
<spirit:description>Output from the GTPE2_COMMON PLL port PLL1OUTCLK.</spirit:description>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
<spirit:master/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CLK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>pll1outclk_out</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:vendorExtensions>
<xilinx:busInterfaceInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pll1outclk_out_out_port" xilinx:dependency="(starts_with(id('PARAM_VALUE.Transceiver'),'GTPE2') and (id('PARAM_VALUE.SupportLevel') = '1'))">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:busInterfaceInfo>
</spirit:vendorExtensions>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>pll1outclk_port</spirit:name>
<spirit:displayName>pll1outclk</spirit:displayName>
<spirit:description>Connect to the GTPE2_COMMON PLL port PLL1OUTCLK.</spirit:description>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CLK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>pll1outclk</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:vendorExtensions>
<xilinx:busInterfaceInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pll1outclk_port" xilinx:dependency="(starts_with(id('PARAM_VALUE.Transceiver'),'GTPE2') and (id('PARAM_VALUE.SupportLevel') = '0'))">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:busInterfaceInfo>
</spirit:vendorExtensions>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>pll1outrefclk_out_port</spirit:name>
<spirit:displayName>pll1outrefclk_out</spirit:displayName>
<spirit:description>Output from the GTPE2_COMMON PLL port PLL1OUTREFCLK</spirit:description>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
<spirit:master/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CLK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>pll1outrefclk_out</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:vendorExtensions>
<xilinx:busInterfaceInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pll1outrefclk_out_port" xilinx:dependency="(starts_with(id('PARAM_VALUE.Transceiver'),'GTPE2') and (id('PARAM_VALUE.SupportLevel') = '1'))">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:busInterfaceInfo>
</spirit:vendorExtensions>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>pll1outrefclk_port</spirit:name>
<spirit:displayName>pll1outrefclk</spirit:displayName>
<spirit:description>Connect to the GTPE2_COMMON PLL REFCLK port PLL1OUTREFCLK</spirit:description>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CLK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>pll1outrefclk</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:vendorExtensions>
<xilinx:busInterfaceInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.pll1outrefclk_port" xilinx:dependency="(starts_with(id('PARAM_VALUE.Transceiver'),'GTPE2') and (id('PARAM_VALUE.SupportLevel') = '0'))">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:busInterfaceInfo>
</spirit:vendorExtensions>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>reset</spirit:name>
<spirit:displayName>reset</spirit:displayName>
<spirit:description>Asynchronous Reset</spirit:description>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>reset</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>POLARITY</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.RESET.POLARITY">ACTIVE_HIGH</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>transceiver_debug0</spirit:name>
<spirit:displayName>transceiver_debug0</spirit:displayName>
<spirit:description>Transceiver Debug Interface</spirit:description>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="display_rxaui" spirit:name="transceiver_debug" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="display_rxaui" spirit:name="transceiver_debug_rtl" spirit:version="1.0"/>
<spirit:master/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>cplllock</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>gt0_cplllock_out</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>dmonitorout</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>gt0_dmonitorout_out</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>eyescandataerror</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>gt0_eyescandataerror_out</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>eyescanreset</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>gt0_eyescanreset_in</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>eyescantrigger</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>gt0_eyescantrigger_in</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>loopback</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>gt0_loopback_in</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>rxbufstatus</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>gt0_rxbufstatus_out</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>rxcdrhold</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>gt0_rxcdrhold_in</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>rxcommadet</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>gt0_rxcommadet_out</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>rxdfelpmreset</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>gt0_rxdfelpmreset_in</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>rxdisperr</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>gt0_rxdisperr_out</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>rxlpmen</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>gt0_rxlpmen_in</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>rxlpmhfhold</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>gt0_rxlpmhfhold_in</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>rxlpmhfovrden</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>gt0_rxlpmhfovrden_in</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>rxlpmlfhold</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>gt0_rxlpmlfhold_in</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>rxlpmlfovrden</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>gt0_rxlpmlfovrden_in</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>rxlpmreset</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>gt0_rxlpmreset_in</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>rxmonitorout</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>gt0_rxmonitorout_out</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>rxmonitorsel</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>gt0_rxmonitorsel_in</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>rxnotintable</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>gt0_rxnotintable_out</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
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<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.c_txdata_width">64</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>c_rxdata_width</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.c_rxdata_width">64</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="boolean">
<spirit:name>c_has_mdio</spirit:name>
<spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.c_has_mdio">true</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="string">
<spirit:name>c_gtwizardSubCoreName</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.c_gtwizardSubCoreName">rxaui_0_gt</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>c_gt_dmonitorout_width</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.c_gt_dmonitorout_width">8</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>c_gt_txdiffctrl_width</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.c_gt_txdiffctrl_width">8</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>c_gt_daddr_width</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.c_gt_daddr_width">9</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="string">
<spirit:name>c_refclkrate</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.c_refclkrate">156.25</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="float">
<spirit:name>c_drpclk_freq</spirit:name>
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.c_drpclk_freq">100.0</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="string">
<spirit:name>c_gt_loc</spirit:name>
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.c_gt_loc">X0Y0 X0Y1</spirit:value>
</spirit:modelParameter>
</spirit:modelParameters>
</spirit:model>
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<spirit:choice>
<spirit:name>choice_list_20920dd1</spirit:name>
<spirit:enumeration>GTH</spirit:enumeration>
<spirit:enumeration>GTY</spirit:enumeration>
</spirit:choice>
<spirit:choice>
<spirit:name>choice_list_4dbacc44</spirit:name>
<spirit:enumeration>125</spirit:enumeration>
<spirit:enumeration>156.25</spirit:enumeration>
<spirit:enumeration>312.5</spirit:enumeration>
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<spirit:choice>
<spirit:name>choice_list_767a41eb</spirit:name>
<spirit:enumeration>Dune</spirit:enumeration>
<spirit:enumeration>Marvell</spirit:enumeration>
</spirit:choice>
<spirit:choice>
<spirit:name>choice_list_949abb3f</spirit:name>
<spirit:enumeration>X0Y0</spirit:enumeration>
</spirit:choice>
<spirit:choice>
<spirit:name>choice_list_e32fe488</spirit:name>
<spirit:enumeration>GTPE2</spirit:enumeration>
<spirit:enumeration>GTXE2</spirit:enumeration>
<spirit:enumeration>GTHE2</spirit:enumeration>
<spirit:enumeration>GTHE3</spirit:enumeration>
<spirit:enumeration>GTYE3</spirit:enumeration>
<spirit:enumeration>GTHE4</spirit:enumeration>
<spirit:enumeration>GTYE4</spirit:enumeration>
</spirit:choice>
<spirit:choice>
<spirit:name>choice_pairs_53749dec</spirit:name>
<spirit:enumeration spirit:text="Include Shared Logic in core">1</spirit:enumeration>
<spirit:enumeration spirit:text="Include Shared Logic in example design">0</spirit:enumeration>
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</spirit:choices>
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<spirit:fileSet>
<spirit:name>xilinx_vhdlinstantiationtemplate_view_fileset</spirit:name>
<spirit:file>
<spirit:name>rxaui_0.vho</spirit:name>
<spirit:userFileType>vhdlTemplate</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>rxaui_0.veo</spirit:name>
<spirit:userFileType>verilogTemplate</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_versioninformation_view_fileset</spirit:name>
<spirit:file>
<spirit:name>doc/rxaui_v4_3_changelog.txt</spirit:name>
<spirit:userFileType>text</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_anylanguagesynthesis_xilinx_com_ip_xaui_12_2__ref_view_fileset</spirit:name>
<spirit:file>
<spirit:name>hdl/xaui_v12_2_rfs.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>xaui_v12_2_7</spirit:logicalName>
</spirit:file>
<spirit:vendorExtensions>
<xilinx:subCoreRef>
<xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="xaui" xilinx:version="12.2" xilinx:isGenerated="true" xilinx:checksum="5c842d26">
<xilinx:mode xilinx:name="copy_mode"/>
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</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
<spirit:file>
<spirit:name>hdl/rxaui_v4_3_rfs.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
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<spirit:file>
<spirit:name>hdl/rxaui_v4_3_rfs.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:logicalName>rxaui_v4_3_7</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>synth/rxaui_0.xdc</spirit:name>
<spirit:userFileType>xdc</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>synth/rxaui_0_ooc.xdc</spirit:name>
<spirit:userFileType>xdc</spirit:userFileType>
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
<spirit:userFileType>USED_IN_out_of_context</spirit:userFileType>
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>synth/rxaui_0_ff_synchronizer.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>synth/rxaui_0_tx_sync_sync_block.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>synth/rxaui_0_tx_sync_sync_pulse.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>tx_sync_manual_vhd.txt</spirit:name>
<spirit:userFileType>text</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>synth/rxaui_0_gt_wrapper_tx_sync_manual.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>synth/rxaui_0_reset_counter.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
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<spirit:file>
<spirit:name>synth/rxaui_0_gt_wrapper_gt.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>synth/rxaui_0_cl_clocking.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>synth/rxaui_0_cl_resets.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
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<spirit:file>
<spirit:name>synth/rxaui_0_block.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
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<spirit:file>
<spirit:name>synth/rxaui_0_support.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>synth/rxaui_0_support_clocking.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>synth/rxaui_0_support_resets.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>synth/rxaui_0_gt_common_wrapper.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
<spirit:file>
<spirit:name>synth/rxaui_0.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
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<spirit:fileSet>
<spirit:name>xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_xaui_12_2__ref_view_fileset</spirit:name>
<spirit:file>
<spirit:name>hdl/xaui_v12_2_rfs.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
<spirit:logicalName>xaui_v12_2_7</spirit:logicalName>
</spirit:file>
<spirit:vendorExtensions>
<xilinx:subCoreRef>
<xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="xaui" xilinx:version="12.2" xilinx:isGenerated="true" xilinx:checksum="1f7a3597">
<xilinx:mode xilinx:name="copy_mode"/>
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</xilinx:subCoreRef>
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</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
<spirit:file>
<spirit:name>hdl/rxaui_v4_3_rfs.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
<spirit:logicalName>rxaui_v4_3_7</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>hdl/rxaui_v4_3_rfs.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
<spirit:logicalName>rxaui_v4_3_7</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>synth/rxaui_0_ff_synchronizer.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>synth/rxaui_0_reset_counter.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>synth/rxaui_0_tx_sync_sync_block.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>synth/rxaui_0_tx_sync_sync_pulse.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>tx_sync_manual_vhd.txt</spirit:name>
<spirit:userFileType>text</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>synth/rxaui_0_gt_wrapper_tx_sync_manual.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>synth/rxaui_0_gt_wrapper_gt.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
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<spirit:file>
<spirit:name>synth/rxaui_0_cl_clocking.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>synth/rxaui_0_cl_resets.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>synth/rxaui_0_block.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>synth/rxaui_0_support.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>synth/rxaui_0_support_clocking.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
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<spirit:file>
<spirit:name>synth/rxaui_0_support_resets.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
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<spirit:name>synth/rxaui_0_gt_common_wrapper.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
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<spirit:fileSet>
<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
<spirit:file>
<spirit:name>synth/rxaui_0.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
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<spirit:fileSet>
<spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
<spirit:file>
<spirit:name>rxaui_0.dcp</spirit:name>
<spirit:userFileType>dcp</spirit:userFileType>
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
<spirit:file>
<spirit:name>rxaui_0_stub.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
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<spirit:file>
<spirit:name>rxaui_0_stub.vhdl</spirit:name>
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<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
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<spirit:description>The Xilinx Reduced Pin 10 Gigabit Attachment Unit Interface (RXAUI) LogiCORE provides a 2-lane high speed serial interface, providing up to 10 Gigabits per second (Gbps) total throughput. Operating at an internal clock speed of 156.25 MHz, the core includes the Dune Networks RXAUI implementation, the XGMII Extender Sublayers (DTE and PHY XGXS), and the 10GBASE-X sublayer, as described in clauses 47 and 48 of IEEE 802.3-2008. The core supports an optional serial MDIO management interface for accessing the IEEE 802.3-2008 clause 45 management registers. The MDIO interface may be omitted to save slice logic, in which case a simplified management interface is provided via bit vectors. The core is designed to seamlessly interface with the 10 Gigabit Ethernet Media Access Controller (XGMAC) LogiCORE via the XGMII.</spirit:description>
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<spirit:name>Component_Name</spirit:name>
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<xilinx:parameterInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Component_Name">true</xilinx:isEnabled>
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<spirit:parameter>
<spirit:name>RXAUI_Mode</spirit:name>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RXAUI_Mode" spirit:choiceRef="choice_list_767a41eb" spirit:order="3" spirit:configGroups="1 UnGrouped">Dune</spirit:value>
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<xilinx:parameterInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.RXAUI_Mode">false</xilinx:isEnabled>
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<spirit:parameter>
<spirit:name>Mdio_Management</spirit:name>
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Mdio_Management" spirit:order="4" spirit:configGroups="1 UnGrouped">true</spirit:value>
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<xilinx:parameterInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Mdio_Management">true</xilinx:isEnabled>
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<spirit:parameter>
<spirit:name>SupportLevel</spirit:name>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.SupportLevel" spirit:choiceRef="choice_pairs_53749dec" spirit:order="5" spirit:configGroups="1 UnGrouped">1</spirit:value>
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<xilinx:parameterInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.SupportLevel">true</xilinx:isEnabled>
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<spirit:parameter>
<spirit:name>TransceiverControl</spirit:name>
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<xilinx:enablement>
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<spirit:parameter>
<spirit:name>Transceiver</spirit:name>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Transceiver" spirit:choiceRef="choice_list_e32fe488" spirit:order="7" spirit:configGroups="1 UnGrouped">GTXE2</spirit:value>
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<xilinx:parameterInfo>
<xilinx:enablement>
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<spirit:name>vu_gt_type</spirit:name>
<spirit:displayName>GT TYPE</spirit:displayName>
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<xilinx:parameterInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.vu_gt_type">false</xilinx:isEnabled>
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<spirit:parameter>
<spirit:name>RefClkRate</spirit:name>
<spirit:displayName>Reference Clock Frequency (MHz)</spirit:displayName>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RefClkRate" spirit:choiceRef="choice_list_4dbacc44" spirit:order="9">156.25</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
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<spirit:parameter>
<spirit:name>DRPCLK_FREQ</spirit:name>
<spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.DRPCLK_FREQ" spirit:order="10">100.0</spirit:value>
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<xilinx:parameterInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.DRPCLK_FREQ">true</xilinx:isEnabled>
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</spirit:parameter>
<spirit:parameter>
<spirit:name>Locations</spirit:name>
<spirit:displayName>Transceiver Location</spirit:displayName>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Locations" spirit:choiceRef="choice_list_949abb3f" spirit:order="11">X0Y0</spirit:value>
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<spirit:vendorExtensions>
<xilinx:coreExtensions>
<xilinx:displayName>RXAUI</xilinx:displayName>
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