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-------------------------------------------------------------------------------
-- Title      : RXAUI Core Level Resets
-- Project    : RXAUI
-------------------------------------------------------------------------------
-- File       : rxaui_0_cl_resets.vhd
-------------------------------------------------------------------------------
-- Description: This module holds the per-core resets for the
--              RXAUI core
-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity rxaui_0_cl_resets is
    port (
      reset               : in  std_logic; -- Asynchronous reset
      clk156              : in  std_logic; -- 156.25MHz Clock derived from GT txoutclk
      uclk_txlock         : in  std_logic; -- PLL is locked (either the GT_COMMON, or GT_CHANNEL)
      reset156            : out  std_logic -- Synchronous reset to clk156
      );
end rxaui_0_cl_resets;
 
architecture rtl of rxaui_0_cl_resets is
  component rxaui_0_ff_synchronizer
    generic
    (
      C_NUM_SYNC_REGS     : integer := 3
    );
    port
    (
      clk                 : in  std_logic;
      data_in             : in std_logic;
      data_out            : out std_logic
    );
  end component;
 
  attribute ASYNC_REG : string;
  attribute shreg_extract : string;
 
  signal reset156_r1      : std_logic;
  signal reset156_r2      : std_logic;
  signal reset156_r3      : std_logic;
  attribute ASYNC_REG of reset156_r1   : signal is "TRUE";
  attribute ASYNC_REG of reset156_r2   : signal is "TRUE";
  attribute ASYNC_REG of reset156_r3   : signal is "TRUE";
 
begin
 
  p_reset : process (clk156)
  begin
    if rising_edge(clk156) then
      if reset = '1' then
        reset156_r1 <= '1';
        reset156_r2 <= '1';
        reset156_r3 <= '1';
      else
        reset156_r1 <= not uclk_txlock;
        reset156_r2 <= reset156_r1;
        reset156_r3 <= reset156_r2;
      end if;
    end if;
  end process;
 
  reset156 <= reset156_r3;
 
end rtl;