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-------------------------------------------------------------------------------
-- Title      : FF Synchronizer
-- Project    : RXAUI
-------------------------------------------------------------------------------
-- File       : rxaui_0_ff_synchronizer.vhd
-------------------------------------------------------------------------------
-- Description: This module provides a parameterizable multi stage
--              FF Synchronizer with appropriate synth attributes
--              to mark ASYNC_REG and prevent SRL inference
-------------------------------------------------------------------------------
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-------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity rxaui_0_ff_synchronizer is
    generic (
      C_NUM_SYNC_REGS  : integer := 3
    );
    port (
      clk              : in  std_logic;
      data_in          : in  std_logic;
      data_out         : out std_logic
      );
end rxaui_0_ff_synchronizer;
 
architecture rtl of rxaui_0_ff_synchronizer is
  signal sync_r : std_logic_vector(C_NUM_SYNC_REGS -1 downto 0) := (others => '0');
 
  --ASYNC_REG attributes
  attribute ASYNC_REG : string;
  attribute shreg_extract : string;
  attribute ASYNC_REG of sync_r        : signal is "TRUE";
  attribute shreg_extract of sync_r    : signal is "no";
 
begin
  process(clk) begin
    if rising_edge(clk) then
      sync_r <= sync_r(C_NUM_SYNC_REGS - 2 downto 0) & data_in;
    end if;
  end process;
 
  data_out <= sync_r(C_NUM_SYNC_REGS - 1);
end rtl;