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-------------------------------------------------------------------------------
-- Title      : Example Design Clocking
-- Project    : RXAUI
-------------------------------------------------------------------------------
-- File       : rxaui_0_support_clocking.vhd
-------------------------------------------------------------------------------
-- Description: This file constains the clocking used by the example design
-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
library unisim;
use unisim.vcomponents.all;
 
entity rxaui_0_support_clocking is
    port (
      refclk_p         : in  std_logic;
      refclk_n         : in  std_logic;
      refclk           : out std_logic
      );
end rxaui_0_support_clocking;
 
architecture rtl of rxaui_0_support_clocking is
 
  signal refclk_p_ibuf : std_logic;
  signal refclk_n_ibuf : std_logic;
 
begin
 
  refclk_p_ibuf_inst : IBUF
  generic map (
    IBUF_LOW_PWR => FALSE,              -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
    IOSTANDARD   => "DEFAULT")         -- Specify the input I/O standard
  port map (
    O            => refclk_p_ibuf,     -- Buffer output
    I            => refclk_p           -- Buffer input (connect directly to top-level port)
  );
 
  refclk_n_ibuf_inst : IBUF
  generic map (
    IBUF_LOW_PWR => FALSE,              -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
    IOSTANDARD   => "DEFAULT")         -- Specify the input I/O standard
  port map (
    O            => refclk_n_ibuf,     -- Buffer output
    I            => refclk_n           -- Buffer input (connect directly to top-level port)
  );
 
  -- Differential Clock Module
  refclk_ibufds : IBUFDS_GTE2
  port map (
    I            => refclk_p_ibuf,
    IB           => refclk_n_ibuf,
    O            => refclk,
    CEB          => '0',
    ODIV2        => open );
 
end rtl;