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-------------------------------------------------------------------------------
-- Title      : Example Design Resets
-- Project    : RXAUI
-------------------------------------------------------------------------------
-- File       : rxaui_0_support_resets.vhd
-------------------------------------------------------------------------------
-- Description: This file constains the resets used by the example design
-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity rxaui_0_support_resets is
    port (
      reset             : in  std_logic;
      dclk              : in  std_logic;
      common_pll_reset  : out std_logic
      );
end rxaui_0_support_resets;
 
architecture rtl of rxaui_0_support_resets is
 
 
  constant COUNT_WIDTH : integer := 8;
  signal counter : unsigned (COUNT_WIDTH-1 downto 0) := (others => '0');
  signal count_d1 : std_logic;
 
  attribute ASYNC_REG : string;
  attribute shreg_extract : string;
 
  signal reset_count_done          : std_logic := '0';
  signal initial_reset             : std_logic := '0';
 
begin
 
 
  -- reset logic - Implement counter to hold resets for a minimum of 500 ns after GSR
  -- This counter is based on worst case 200MHz DCLK
  process(dclk) begin
    if rising_edge(dclk) then
      if (counter(COUNT_WIDTH-1) = '0') then
        counter <= counter + 1;
      end if;
    end if;
  end process;
 
  process(dclk) begin
    if rising_edge(dclk) then
      count_d1 <= std_logic(counter(COUNT_WIDTH -1));
    end if;
  end process;
 
  process(dclk) begin
    if rising_edge(dclk) then
      if ((count_d1 = '0') and (std_logic(counter(COUNT_WIDTH-1)) = '1')) then
        initial_reset <= std_logic(counter(COUNT_WIDTH -1));
      else
        initial_reset <= '0';
      end if;
    end if;
  end process;
  reset_count_done <= std_logic(counter(COUNT_WIDTH -1));
 
  -- Reset the common PLL on startup, and every reset (after 500ns has elapsed)
  common_pll_reset <= (reset and reset_count_done) or initial_reset;
 
end rtl;