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https://opencores.org/ocsvn/xgate/xgate/trunk
Subversion Repositories xgate
[/] [xgate/] [trunk/] [sim/] [verilog/] [run/] [run_iverilog] - Rev 70
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#!/bin/csh
set xgate = ../../..
set bench = $xgate/bench
set wave_dir = $xgate/sim/rtl_sim/xgate_verilog/waves
iverilog \
\
-I $bench/verilog \
-I $xgate/rtl/verilog \
\
-o xgate_compiled \
-D WAVES_V \
\
$xgate/rtl/verilog/xgate_top.v \
$xgate/rtl/verilog/xgate_wbs_bus.v \
$xgate/rtl/verilog/xgate_wbm_bus.v \
$xgate/rtl/verilog/xgate_regs.v \
$xgate/rtl/verilog/xgate_risc.v \
$xgate/rtl/verilog/xgate_irq_encode.v \
\
$bench/verilog/wb_master_model.v \
$bench/verilog/ram.v \
$bench/verilog/tst_bench_top.v
@ good_compile = $status
if ($good_compile == 0) then
echo "Compile was Good"
vvp xgate_compiled -lxt2
else
echo "Compile Failed"
endif
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