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[/] [xge_mac/] [trunk/] [sim/] [proto_systemverilog/] [irun.log] - Rev 25

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irun: 09.20-p007: (c) Copyright 1995-2009 Cadence Design Systems, Inc.
TOOL:   irun    09.20-p007: Started on Oct 28, 2012 at 18:11:47 PDT
irun
        ../../verification/macCoreInterface.sv
        ../../verification/testbench.sv
        ../../rtl/verilog/fault_sm.v
        ../../rtl/verilog/generic_fifo_ctrl.v
        ../../rtl/verilog/generic_fifo.v
        ../../rtl/verilog/generic_mem_medium.v
        ../../rtl/verilog/generic_mem_small.v
        ../../rtl/verilog/meta_sync_single.v
        ../../rtl/verilog/meta_sync.v
        ../../rtl/verilog/rx_data_fifo.v
        ../../rtl/verilog/rx_dequeue.v
        ../../rtl/verilog/rx_enqueue.v
        ../../rtl/verilog/rx_hold_fifo.v
        ../../rtl/verilog/sync_clk_core.v
        ../../rtl/verilog/sync_clk_wb.v
        ../../rtl/verilog/sync_clk_xgmii_tx.v
        ../../rtl/verilog/tx_data_fifo.v
        ../../rtl/verilog/tx_dequeue.v
        ../../rtl/verilog/tx_enqueue.v
        ../../rtl/verilog/tx_hold_fifo.v
        ../../rtl/verilog/wishbone_if.v
        ../../rtl/verilog/xge_mac.v
        testcase.sv
        +incdir+../../rtl/include/
        +svseed=random
irun: *E,FILEMIS: Cannot find the provided file testcase.sv.
TOOL:   irun    09.20-p007: Exiting on Oct 28, 2012 at 18:11:48 PDT  (total: 00:00:01)

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