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[/] [xge_mac/] [trunk/] [sim/] [proto_systemverilog/] [runsim] - Rev 22
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vcs +vcs+lic+wait -sverilog -R -l vcs.log \-override_timescale=1ps/1ps \../../rtl/verilog/*.v \+incdir+../../rtl/include \../../testbench/verilog/tb_xge_mac.sv