Subversion Repositories xmatchpro

JDF G
PROJECT level1r
DESIGN level1r
DEVFAM virtex4
DEVICE xc4vlx25
DEVSPEED -10
DEVPKG ff668
DEVTOPLEVELMODULETYPE HDL
DEVSIMULATOR Modelsim
DEVGENERATEDSIMULATIONMODEL VHDL
SOURCE ..\..\src\reg_temp.vhd
SOURCE ..\..\src\tech_package.vhd
SOURCE ..\..\src\mux_ram.vhd
SOURCE ..\..\src\sync_ram_register.vhd
SOURCE ..\..\src\location_equal.vhd
#SOURCE ..\..\src\ff_finish_decoding.vhd
SOURCE ..\..\src\out_register.vhd
SOURCE ..\..\src\decode_mt_2.vhd
SOURCE ..\..\src\decode4_16_inv.vhd
SOURCE ..\..\src\decomp_assem_9.vhd
SOURCE ..\..\src\decode_miss_2.vhd
SOURCE ..\..\src\length_selection_2.vhd
SOURCE ..\..\src\max_pbc_length_2.vhd
SOURCE ..\..\src\mask_bit.vhd
SOURCE ..\..\src\mask_word.vhd
SOURCE ..\..\src\full_match_d.vhd
SOURCE ..\..\src\miss_type_coder.vhd
SOURCE ..\..\src\decomp_decode_4.vhd
SOURCE ..\..\src\latch6.vhd
SOURCE ..\..\src\latch7.vhd
SOURCE ..\..\src\latch133.vhd
SOURCE ..\..\src\pointer_first.vhd
SOURCE ..\..\src\pointer_1.vhd
SOURCE ..\..\src\pointer_2.vhd
SOURCE ..\..\src\pointer_3.vhd
SOURCE ..\..\src\pointer_4.vhd
SOURCE ..\..\src\pointer_5.vhd
SOURCE ..\..\src\pointer_6.vhd
SOURCE ..\..\src\pointer_7.vhd
SOURCE ..\..\src\pointer_8.vhd
SOURCE ..\..\src\pointer_9.vhd
SOURCE ..\..\src\pointer_10.vhd
SOURCE ..\..\src\pointer_11.vhd
SOURCE ..\..\src\pointer_12.vhd
SOURCE ..\..\src\pointer_13.vhd
SOURCE ..\..\src\pointer_14.vhd
SOURCE ..\..\src\pointer_15.vhd
SOURCE ..\..\src\pointer_array.vhd
SOURCE ..\..\src\buffer_counter_write_9bits.vhd
SOURCE ..\..\src\buffer_counter_read_9bits.vhd
SOURCE ..\..\src\crc_unit_c_32.vhd
SOURCE ..\..\src\crc_unit_d_32.vhd
#SOURCE ..\..\src\cam_bit_first.vhd
SOURCE ..\..\src\input_counter_9bits.vhd
#SOURCE ..\..\src\cam_byte_first.vhd
SOURCE ..\..\src\cam_bit.vhd
SOURCE ..\..\src\cam_byte.vhd
#SOURCE ..\..\src\cam_word_first.vhd
SOURCE ..\..\src\cam_word_zero.vhd
SOURCE ..\..\src\cam_array_zero.vhd
SOURCE ..\..\src\lc_assembler.vhd
SOURCE ..\..\src\mc_mux_3d.vhd
SOURCE ..\..\src\mc_mux_3c.vhd
SOURCE ..\..\src\mg_logic_2.vhd
SOURCE ..\..\src\mld_decode.vhd
SOURCE ..\..\src\mld_dprop_5.vhd
SOURCE ..\..\src\ob_assem.vhd
SOURCE ..\..\src\PIPELINE_R1_D.vhd
SOURCE ..\..\src\shift_literal.vhd
SOURCE ..\..\src\oda_cell_2_d.vhd
SOURCE ..\..\src\oda_cell_2_d_1.vhd
SOURCE ..\..\src\oda_cell_2.vhd
SOURCE ..\..\src\oda_register_d.vhd
SOURCE ..\..\src\oda_register.vhd
SOURCE ..\..\src\PIPELINE_R2_D.vhd
SOURCE ..\..\src\rli_counter_d.vhd
SOURCE ..\..\src\rli_counter_c.vhd
SOURCE ..\..\src\RLI_DR.vhd
SOURCE ..\..\src\RLI_DCU.vhd
SOURCE ..\..\src\mt_coder.vhd
SOURCE ..\..\src\ob_assembler.vhd
SOURCE ..\..\src\ov_latch.vhd
SOURCE ..\..\src\pc_generate.vhd
SOURCE ..\..\src\nfl_counters2.vhd
SOURCE ..\..\src\mld_dprop.vhd
SOURCE ..\..\src\mld_logic_3_1_2.vhd
SOURCE ..\..\src\mld_logic_3_2_2.vhd
SOURCE ..\..\src\cm_assembler.vhd
SOURCE ..\..\src\cml_assembler.vhd
SOURCE ..\..\src\csm_c_2.vhd
SOURCE ..\..\src\csm_d.vhd
SOURCE ..\..\src\latch98.vhd
SOURCE ..\..\src\PIPELINE_R0.vhd
SOURCE ..\..\src\PIPELINE_R1.vhd
SOURCE ..\..\src\PIPELINE_R4.vhd
#SOURCE ..\..\src\ff_v3_delay.vhd
SOURCE ..\..\src\bsl_tc_2_c.vhd
SOURCE ..\..\src\bsl_tc_2_d.vhd
SOURCE ..\..\src\c_bs_counter_c.vhd
SOURCE ..\..\src\c_bs_counter_d.vhd
SOURCE ..\..\src\encode16_4.vhd
SOURCE ..\..\src\CODING_BUFFER_CU.vhd
SOURCE ..\..\src\decode_logic_pbc.vhd
SOURCE ..\..\src\sreg.vhd
SOURCE ..\..\src\count_delay.vhd
SOURCE ..\..\src\rli_cr.vhd
SOURCE ..\..\src\rli_ccu.vhd
SOURCE ..\..\src\rli_coding_logic.vhd
SOURCE ..\..\src\level2_4d_pbc.vhd
SOURCE ..\..\src\level2_4ca.vhd
SOURCE ..\..\src\DECODING_BUFFER_CU_2.vhd
SOURCE ..\..\src\BUFFER_COUNTER_READ.vhd
SOURCE ..\..\src\BUFFER_COUNTER_WRITE.vhd
SOURCE ..\..\src\DECODING_BUFFER_32_64_2.vhd
SOURCE ..\..\src\CODING_BUFFER_64_32.vhd
SOURCE ..\..\src\control_reg.vhd
SOURCE ..\..\src\reg_file_c.vhd
SOURCE ..\..\src\reg_file_d.vhd
SOURCE ..\..\src\parser.vhd
SOURCE ..\..\src\parser_register.vhd
SOURCE ..\..\src\parser_concatenator.vhd
SOURCE ..\..\src\parsing_unit.vhd
SOURCE ..\..\src\input_counter.vhd
SOURCE ..\..\src\input_buffer_cu.vhd
SOURCE ..\..\src\input_buffer_32_32.vhd
SOURCE ..\..\src\assembler.vhd
SOURCE ..\..\src\assembler_register.vhd
SOURCE ..\..\src\assembling_unit.vhd
SOURCE ..\..\src\output_buffer_cu.vhd
SOURCE ..\..\src\output_buffer_32_32.vhd
#SOURCE ..\..\src\crc_unit_c.vhd
#SOURCE ..\..\src\crc_unit_d.vhd
SOURCE ..\..\src\level1rc.vhd
SOURCE ..\..\src\level1rd.vhd
SOURCE ..\..\src\level1r.vhd
SOURCE ..\..\src\tb_level1cr.vhd
SUBLIB xil_lib VhdlLibrary vhdl
LIBFILE ..\..\lib\xil_lib\DP_RAM_XILINX_256.vhd xil_lib vhdl
LIBFILE ..\..\lib\xil_lib\DP_RAM_XILINX_512.vhd xil_lib vhdl
LIBFILE ..\..\lib\xil_lib\DP_RAM_XILINX_MASK.vhd xil_lib vhdl
LIBFILE ..\..\lib\xil_lib\xil_comp.vhd xil_lib vhdl
SUBLIB dzx VhdlLibrary vhdl
LIBFILE ..\..\lib\dzx\attributes_pkg.vhd dzx vhdl
LIBFILE ..\..\lib\dzx\bit_arith_pkg.vhd dzx vhdl
LIBFILE ..\..\lib\dzx\bit_arith_pkg_body.vhd dzx vhdl
LIBFILE ..\..\lib\dzx\bit_utils_pkg.vhd dzx vhdl
LIBFILE ..\..\lib\dzx\bit_utils_pkg_body.vhd dzx vhdl
SUBLIB work VhdlLibrary vhdl