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[/] [xmatchpro/] [trunk/] [xmw4-comdec/] [xmatch_sim7/] [Fifo_test.xise] - Rev 9
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xil_pn:name="Implementation" xil_pn:seqID="55"/></file><file xil_pn:name="src/pointer_1.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="33"/><association xil_pn:name="Implementation" xil_pn:seqID="33"/></file><file xil_pn:name="src/pointer_2.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/><association xil_pn:name="Implementation" xil_pn:seqID="26"/></file><file xil_pn:name="src/pointer_3.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/><association xil_pn:name="Implementation" xil_pn:seqID="25"/></file><file xil_pn:name="src/pointer_4.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/><association xil_pn:name="Implementation" xil_pn:seqID="24"/></file><file xil_pn:name="src/pointer_5.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/><association xil_pn:name="Implementation" xil_pn:seqID="23"/></file><file xil_pn:name="src/pointer_6.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/><association xil_pn:name="Implementation" xil_pn:seqID="22"/></file><file xil_pn:name="src/pointer_7.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/><association xil_pn:name="Implementation" xil_pn:seqID="21"/></file><file xil_pn:name="src/pointer_8.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/><association xil_pn:name="Implementation" xil_pn:seqID="20"/></file><file xil_pn:name="src/pointer_9.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/><association xil_pn:name="Implementation" xil_pn:seqID="19"/></file><file xil_pn:name="src/pointer_10.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="32"/><association xil_pn:name="Implementation" xil_pn:seqID="32"/></file><file xil_pn:name="src/pointer_11.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="31"/><association xil_pn:name="Implementation" xil_pn:seqID="31"/></file><file xil_pn:name="src/pointer_12.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/><association xil_pn:name="Implementation" xil_pn:seqID="30"/></file><file xil_pn:name="src/pointer_13.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="29"/><association xil_pn:name="Implementation" xil_pn:seqID="29"/></file><file xil_pn:name="src/pointer_14.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/><association xil_pn:name="Implementation" xil_pn:seqID="28"/></file><file xil_pn:name="src/pointer_15.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/><association xil_pn:name="Implementation" xil_pn:seqID="27"/></file><file xil_pn:name="src/pointer_array.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="54"/><association xil_pn:name="Implementation" xil_pn:seqID="54"/></file><file xil_pn:name="src/pointer_first.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/><association xil_pn:name="Implementation" xil_pn:seqID="18"/></file><file xil_pn:name="src/reg_file_c.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="107"/><association xil_pn:name="Implementation" xil_pn:seqID="107"/></file><file xil_pn:name="src/reg_file_d.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="106"/><association xil_pn:name="Implementation" xil_pn:seqID="106"/></file><file xil_pn:name="src/reg_temp.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="53"/><association xil_pn:name="Implementation" xil_pn:seqID="53"/></file><file xil_pn:name="src/RLI_CCU.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/><association xil_pn:name="Implementation" xil_pn:seqID="17"/></file><file xil_pn:name="src/RLI_coding_logic.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="52"/><association xil_pn:name="Implementation" xil_pn:seqID="52"/></file><file xil_pn:name="src/rli_counter_c.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="51"/><association xil_pn:name="Implementation" xil_pn:seqID="51"/></file><file xil_pn:name="src/rli_counter_d.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="50"/><association xil_pn:name="Implementation" xil_pn:seqID="50"/></file><file xil_pn:name="src/RLI_CR.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/><association xil_pn:name="Implementation" xil_pn:seqID="16"/></file><file xil_pn:name="src/RLI_DCU.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/><association xil_pn:name="Implementation" xil_pn:seqID="15"/></file><file xil_pn:name="src/RLI_DR.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/><association xil_pn:name="Implementation" xil_pn:seqID="14"/></file><file xil_pn:name="src/shift_literal.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/><association xil_pn:name="Implementation" xil_pn:seqID="13"/></file><file xil_pn:name="src/sreg.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="49"/><association xil_pn:name="Implementation" xil_pn:seqID="49"/></file><file xil_pn:name="src/sync_ram_register.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="48"/><association xil_pn:name="Implementation" xil_pn:seqID="48"/></file><file xil_pn:name="src/tech_package.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="47"/><association xil_pn:name="Implementation" xil_pn:seqID="47"/></file><file xil_pn:name="lib/dzx/attributes_pkg.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/><association xil_pn:name="Implementation" xil_pn:seqID="12"/><library xil_pn:name="dzx"/></file><file xil_pn:name="lib/dzx/bit_arith_pkg.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/><association xil_pn:name="Implementation" xil_pn:seqID="1"/><library xil_pn:name="dzx"/></file><file xil_pn:name="lib/dzx/bit_arith_pkg_body.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/><association xil_pn:name="Implementation" xil_pn:seqID="4"/><library xil_pn:name="dzx"/></file><file xil_pn:name="lib/dzx/bit_utils_pkg.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/><association xil_pn:name="Implementation" xil_pn:seqID="3"/><library xil_pn:name="dzx"/></file><file xil_pn:name="lib/dzx/bit_utils_pkg_body.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/><association xil_pn:name="Implementation" xil_pn:seqID="11"/><library xil_pn:name="dzx"/></file><file xil_pn:name="lib/xil_lib/DP_RAM_XILINX_256.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="105"/><association xil_pn:name="Implementation" xil_pn:seqID="105"/><library xil_pn:name="xil_lib"/></file><file xil_pn:name="lib/xil_lib/DP_RAM_XILINX_512.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="104"/><association xil_pn:name="Implementation" xil_pn:seqID="104"/><library xil_pn:name="xil_lib"/></file><file xil_pn:name="lib/xil_lib/DP_RAM_XILINX_MASK.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="103"/><association xil_pn:name="Implementation" xil_pn:seqID="103"/><library xil_pn:name="xil_lib"/></file><file xil_pn:name="lib/xil_lib/xil_comp.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="102"/><association xil_pn:name="Implementation" xil_pn:seqID="102"/><library xil_pn:name="xil_lib"/></file><file xil_pn:name="tb.vhd" xil_pn:type="FILE_VHDL"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="130"/><association xil_pn:name="PostMapSimulation" xil_pn:seqID="215"/><association xil_pn:name="PostRouteSimulation" xil_pn:seqID="215"/><association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="215"/></file><file xil_pn:name="ipcore_dir/fifo_32x512.xco" xil_pn:type="FILE_COREGEN"><association xil_pn:name="BehavioralSimulation" xil_pn:seqID="128"/><association xil_pn:name="Implementation" xil_pn:seqID="230"/></file><file xil_pn:name="ipcore_dir/fifo_32x512.xise" xil_pn:type="FILE_COREGENISE"><association xil_pn:name="Implementation" xil_pn:seqID="231"/></file></files><properties><property xil_pn:name="AES Initial Vector virtex5" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="AES Initial Vector virtex6" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="AES Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="AES Key (Hex String) virtex6" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/><property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/><property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/><property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/><property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/><property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="BPI Reads Per Page" xil_pn:value="1" xil_pn:valueState="default"/><property xil_pn:name="BPI Sync Mode" xil_pn:value="Disable" xil_pn:valueState="default"/><property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/><property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/><property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/><property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/><property xil_pn:name="Change Device Speed To" xil_pn:value="-2" xil_pn:valueState="default"/><property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-2" xil_pn:valueState="default"/><property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/><property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/><property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/><property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/><property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/><property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/><property xil_pn:name="Configuration Pin Busy" xil_pn:value="Pull Up" xil_pn:valueState="default"/><property xil_pn:name="Configuration Pin CS" xil_pn:value="Pull Up" xil_pn:valueState="default"/><property xil_pn:name="Configuration Pin DIn" xil_pn:value="Pull Up" xil_pn:valueState="default"/><property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/><property xil_pn:name="Configuration Pin HSWAPEN" xil_pn:value="Pull Up" xil_pn:valueState="default"/><property xil_pn:name="Configuration Pin Init" xil_pn:value="Pull Up" xil_pn:valueState="default"/><property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/><property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/><property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/><property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/><property xil_pn:name="Configuration Pin RdWr" xil_pn:value="Pull Up" xil_pn:valueState="default"/><property xil_pn:name="Configuration Rate virtex5" xil_pn:value="3" xil_pn:valueState="default"/><property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/><property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Cycles for First BPI Page Read" xil_pn:value="1" xil_pn:valueState="default"/><property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/><property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/><property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/><property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/><property xil_pn:name="Device" xil_pn:value="xc7vx485t" xil_pn:valueState="non-default"/><property xil_pn:name="Device Family" xil_pn:value="Virtex7" xil_pn:valueState="non-default"/><property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-2" xil_pn:valueState="default"/><property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Disable JTAG Connection" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Do Not Escape Signal and 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xil_pn:valueState="default"/><property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/><property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="Off" xil_pn:valueState="default"/><property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/><property xil_pn:name="Encrypt Bitstream" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Encrypt Bitstream virtex6" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Encrypt Key Select virtex6" xil_pn:value="BBRAM" xil_pn:valueState="default"/><property xil_pn:name="Equivalent Register Removal" xil_pn:value="true" xil_pn:valueState="default"/><property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/><property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/><property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/><property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Extra Cost Tables Map virtex6" xil_pn:value="0" xil_pn:valueState="default"/><property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/><property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/><property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/><property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/><property xil_pn:name="Fallback Reconfiguration" xil_pn:value="Enable" xil_pn:valueState="default"/><property xil_pn:name="Fallback Reconfiguration virtex7" xil_pn:value="Disable" xil_pn:valueState="default"/><property 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