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[/] [xmatchpro/] [trunk/] [xmw4-comdec/] [xmatch_sim7/] [ipcore_dir/] [fifo_32x512/] [simulation/] [timing/] [wave_ncsim.sv] - Rev 9
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#--------------------------------------------------------------------------------
#--
#-- FIFO Generator Core Demo Testbench
#--
#--------------------------------------------------------------------------------
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
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# international copyright and other intellectual property
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# PART OF THIS FILE AT ALL TIMES.
# Filename: wave_ncsim.sv
#
# Description:
# This is the IUS wave form file.
#
#--------------------------------------------------------------------------------
window new WaveWindow -name "Waves for FIFO Generator Example Design"
waveform using "Waves for FIFO Generator Example Design"
waveform add -signals /fifo_32x512_tb/fifo_32x512_synth_inst/fifo_32x512_inst/RST
waveform add -label WRITE
waveform add -signals /fifo_32x512_tb/fifo_32x512_synth_inst/fifo_32x512_inst/WR_CLK
waveform add -signals /fifo_32x512_tb/fifo_32x512_synth_inst/fifo_32x512_inst/WR_EN
waveform add -signals /fifo_32x512_tb/fifo_32x512_synth_inst/fifo_32x512_inst/FULL
waveform add -label READ
waveform add -signals /fifo_32x512_tb/fifo_32x512_synth_inst/fifo_32x512_inst/RD_CLK
waveform add -signals /fifo_32x512_tb/fifo_32x512_synth_inst/fifo_32x512_inst/RD_EN
waveform add -signals /fifo_32x512_tb/fifo_32x512_synth_inst/fifo_32x512_inst/EMPTY
console submit -using simulator -wait no "run"