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[/] [xucpu/] [trunk/] [src/] [components/] [BRAM/] [RAM.vhdl] - Rev 41
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-- Copyright 2015, Jürgen Defurne -- -- This file is part of the Experimental Unstable CPU System. -- -- The Experimental Unstable CPU System Is free software: you can redistribute -- it and/or modify it under the terms of the GNU Lesser General Public License -- as published by the Free Software Foundation, either version 3 of the -- License, or (at your option) any later version. -- -- The Experimental Unstable CPU System is distributed in the hope that it will -- be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser -- General Public License for more details. -- -- You should have received a copy of the GNU Lesser General Public License -- along with Experimental Unstable CPU System. If not, see -- http://www.gnu.org/licenses/lgpl.txt. -- This package is the main interface to the memory. When defining -- different sizes, this package generates the main component. -- The components themselves are responsible for using the contents -- of the passed file name to initialise the memory array. LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; PACKAGE RAM IS COMPONENT memory IS GENERIC ( filename : STRING := ""; w_data : NATURAL RANGE 1 TO 32 := 16; w_addr : NATURAL RANGE 8 TO 15 := 10); PORT ( clk : IN STD_LOGIC; we : IN STD_LOGIC; a1 : IN STD_LOGIC_VECTOR(w_addr - 1 DOWNTO 0); -- Data port address a2 : IN STD_LOGIC_VECTOR(w_addr - 1 DOWNTO 0); -- Instruction port address d1 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0); -- Data port input q1 : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0); -- Data port output q2 : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0)); -- Instruction port output END COMPONENT memory; END PACKAGE RAM; LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; USE work.ram_parts.ALL; USE work.hexio.ALL; ENTITY memory IS -- Memory component based upon Xilinx Spartan-6 block RAM -- Maximum capacity is 16k words -- This component can be initialised by passing a file name as a generic -- parameter. GENERIC ( filename : STRING := ""; w_data : NATURAL RANGE 1 TO 32 := 16; w_addr : NATURAL RANGE 8 TO 15 := 10); PORT ( clk : IN STD_LOGIC; we : IN STD_LOGIC; a1 : IN STD_LOGIC_VECTOR(w_addr - 1 DOWNTO 0); -- Data port address a2 : IN STD_LOGIC_VECTOR(w_addr - 1 DOWNTO 0); -- Instruction port address d1 : IN STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0); -- Data port input q1 : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0); -- Data port output q2 : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0)); -- Instruction port output END memory; ARCHITECTURE Structural OF memory IS CONSTANT dummy : INTEGER := notify_f("Initialisation of memory component starts"); BEGIN -- Structural SMALL_MEM : IF w_addr >= 8 AND w_addr <= 14 GENERATE MEM0 : RAM_GENERIC GENERIC MAP ( filename => filename, w_data => w_data, w_addr => w_addr) PORT MAP ( clk => clk, we => we, a1 => a1, a2 => a2, d1 => d1, q1 => q1, q2 => q2); END GENERATE SMALL_MEM; LARGE_MEM : IF w_addr = 15 GENERATE MEM1 : RAM32K GENERIC MAP ( filename => filename, w_data => w_data) PORT MAP ( clk => clk, we => we, a1 => a1, a2 => a2, d1 => d1, q1 => q1, q2 => q2); END GENERATE LARGE_MEM; END Structural;
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