Subversion Repositories xucpu

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
PACKAGE S2LIB IS
 
  COMPONENT S2ARB IS
    PORT (
      I_RD_ICC          : IN  STD_LOGIC;
      I_WR_ICC          : IN  STD_LOGIC;
      I_RD_DCC          : IN  STD_LOGIC;
      I_WR_DCC          : IN  STD_LOGIC;
      O_ADDRESS_MUX_SEL : OUT STD_LOGIC;
      O_ACK_ICC         : OUT STD_LOGIC;
      O_ACK_DCC         : OUT STD_LOGIC;
      CLK               : IN  STD_LOGIC;
      RST               : IN  STD_LOGIC);
  END COMPONENT S2ARB;
 
  COMPONENT S2ICC IS
    PORT (
      CLK               : IN  STD_LOGIC;
      RST               : IN  STD_LOGIC;
      O_ADDRESS         : OUT STD_LOGIC_VECTOR(14 DOWNTO 0);
      O_DATA            : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
      O_RD              : OUT STD_LOGIC;
      O_WR              : OUT STD_LOGIC;
      I_ACK             : IN  STD_LOGIC;
      I_ADDRESS         : IN  STD_LOGIC_VECTOR(14 DOWNTO 0);
      I_DATA            : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
      I_RD              : IN  STD_LOGIC;
      I_WR              : IN  STD_LOGIC;
      I_CPU_IF          : IN  STD_LOGIC;
      I_CPU_INSTR_ADDR  : IN  STD_LOGIC_VECTOR(14 DOWNTO 0);
      O_CPU_INSTRUCTION : OUT STD_LOGIC_VECTOR(15 DOWNTO 0));
  END COMPONENT S2ICC;
 
  COMPONENT S2DCC IS
    PORT (
      CLK             : IN  STD_LOGIC;
      RST             : IN  STD_LOGIC;
      O_ADDRESS       : OUT STD_LOGIC_VECTOR(14 DOWNTO 0);
      O_DATA          : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
      O_RD            : OUT STD_LOGIC;
      O_WR            : OUT STD_LOGIC;
      I_ACK           : IN  STD_LOGIC;
      I_ADDRESS       : IN  STD_LOGIC_VECTOR(14 DOWNTO 0);
      I_DATA          : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
      I_RD              : IN  STD_LOGIC;
      I_WR              : IN  STD_LOGIC;
      I_CPU_RD        : IN  STD_LOGIC;
      I_CPU_WR        : IN  STD_LOGIC;
      I_CPU_DATA_ADDR : IN  STD_LOGIC_VECTOR(14 DOWNTO 0);
      I_CPU_DATA      : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
      O_CPU_DATA      : OUT STD_LOGIC_VECTOR(15 DOWNTO 0));
  END COMPONENT S2DCC;
 
  COMPONENT S2CPU IS
    PORT (
      CLK           : IN  STD_LOGIC;
      RST           : IN  STD_LOGIC;
      O_IF          : OUT STD_LOGIC;
      O_INSTR_ADDR  : OUT STD_LOGIC_VECTOR(14 DOWNTO 0);
      I_INSTRUCTION : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
      O_RD          : OUT STD_LOGIC;
      O_WR          : OUT STD_LOGIC;
      O_DATA_ADDR   : OUT STD_LOGIC_VECTOR(14 DOWNTO 0);
      O_DATA        : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
      I_DATA        : IN  STD_LOGIC_VECTOR(15 DOWNTO 0));
  END COMPONENT S2CPU;
 
  COMPONENT S2MEM IS
    PORT (
      CLK       : IN  STD_LOGIC;
      RST       : IN  STD_LOGIC;
      I_RD      : IN  STD_LOGIC;
      I_WR      : IN  STD_LOGIC;
      I_ADDRESS : IN  STD_LOGIC_VECTOR(14 DOWNTO 0);
      I_DATA    : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
      O_DATA    : OUT STD_LOGIC_VECTOR(15 DOWNTO 0));
  END COMPONENT S2MEM;
 
END PACKAGE S2LIB;