Subversion Repositories xucpu

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
ENTITY instruction_cache_control IS
 
  PORT (
    instruction_fetch   : IN  STD_LOGIC;
    instruction_ack     : OUT STD_LOGIC;
    bus_request         : OUT STD_LOGIC;
    bus_ack             : IN  STD_LOGIC;
    bus_wait            : IN  STD_LOGIC;
    instruction_address : IN  STD_LOGIC_VECTOR(14 DOWNTO 0);
    instruction         : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
    address_bus         : OUT STD_LOGIC_VECTOR(14 DOWNTO 0);
    data_bus            : IN  STD_LOGIC_VECTOR(15 DOWNTO 0));
 
END ENTITY instruction_cache_control;
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
ENTITY instruction_cache IS
 
  PORT (
    valid       : IN  STD_LOGIC;
    tag         : IN  STD_LOGIC_VECTOR(2 DOWNTO 0);
    row_address : IN  STD_LOGIC_VECTOR(8 DOWNTO 0);
    col_address : IN  STD_LOGIC_VECTOR(2 DOWNTO 0);
    hit         : OUT STD_LOGIC;
    wr          : IN  STD_LOGIC;
    wr_instr    : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
    rd_instr    : OUT STD_LOGIC_VECTOR(15 DOWNTO 0));
 
END ENTITY instruction_cache;
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
ENTITY instruction_fetch IS
 
  PORT (
    instruction_fetch   : OUT STD_LOGIC;
    instruction_ack     : IN  STD_LOGIC;
    instruction_address : OUT STD_LOGIC_VECTOR(14 DOWNTO 0);
    instruction         : IN  STD_LOGIC_VECTOR(15 DOWNTO 0));
 
END ENTITY instruction_fetch;
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
ENTITY system_bus IS
 
  PORT (
    address_bus_src : IN  STD_LOGIC_VECTOR(14 DOWNTO 0);
    data_bus_src    : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
    bus_request     : IN  STD_LOGIC;
    bus_ack         : OUT STD_LOGIC;
    bus_wait        : OUT STD_LOGIC;
    address_bus_out : OUT STD_LOGIC_VECTOR(14 DOWNTO 0);
    data_bus_out    : OUT STD_LOGIC_VECTOR(15 DOWNTO 0));
 
END ENTITY system_bus;