Subversion Repositories xucpu

<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
   <wave_state>
   </wave_state>
   <db_ref_list>
      <db_ref path="/home/jurgen/Projects/lisp/harddev/system_sim_isim_par.wdb" id="1" type="auto">
         <top_modules>
            <top_module name="std_logic_1164" />
            <top_module name="std_logic_arith" />
            <top_module name="std_logic_signed" />
            <top_module name="std_logic_textio" />
            <top_module name="std_logic_unsigned" />
            <top_module name="system_sim" />
            <top_module name="textio" />
            <top_module name="vcomponents" />
            <top_module name="vital_primitives" />
            <top_module name="vital_timing" />
            <top_module name="vpackage" />
         </top_modules>
      </db_ref>
   </db_ref_list>
   <WVObjectSize size="21" />
   <wvobject fp_name="/system_sim/clock" type="logic" db_ref_id="1">
      <obj_property name="ElementShortName">clock</obj_property>
      <obj_property name="ObjectShortName">clock</obj_property>
   </wvobject>
   <wvobject fp_name="/system_sim/reset" type="logic" db_ref_id="1">
      <obj_property name="ElementShortName">reset</obj_property>
      <obj_property name="ObjectShortName">reset</obj_property>
   </wvobject>
   <wvobject fp_name="/system_sim/uut/sys_clk" type="logic" db_ref_id="1">
      <obj_property name="ElementShortName">sys_clk</obj_property>
      <obj_property name="ObjectShortName">sys_clk</obj_property>
   </wvobject>
   <wvobject fp_name="/system_sim/uut/sys_rst" type="logic" db_ref_id="1">
      <obj_property name="ElementShortName">sys_rst</obj_property>
      <obj_property name="ObjectShortName">sys_rst</obj_property>
   </wvobject>
   <wvobject fp_name="/system_sim/uut/int_rst" type="logic" db_ref_id="1">
      <obj_property name="ElementShortName">int_rst</obj_property>
      <obj_property name="ObjectShortName">int_rst</obj_property>
   </wvobject>
   <wvobject fp_name="/system_sim/uut/DP1/addr_out" type="array" db_ref_id="1">
      <obj_property name="ElementShortName">addr_out[14:0]</obj_property>
      <obj_property name="ObjectShortName">addr_out[14:0]</obj_property>
   </wvobject>
   <wvobject fp_name="/system_sim/uut/address" type="array" db_ref_id="1">
      <obj_property name="ElementShortName">address[14:0]</obj_property>
      <obj_property name="ObjectShortName">address[14:0]</obj_property>
   </wvobject>
   <wvobject fp_name="/system_sim/uut/MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram/addra" type="array" db_ref_id="1">
      <obj_property name="ElementShortName">addra[13:0]</obj_property>
      <obj_property name="ObjectShortName">addra[13:0]</obj_property>
   </wvobject>
   <wvobject fp_name="/system_sim/uut/databus_in" type="array" db_ref_id="1">
      <obj_property name="ElementShortName">databus_in[15:0]</obj_property>
      <obj_property name="ObjectShortName">databus_in[15:0]</obj_property>
   </wvobject>
   <wvobject fp_name="/system_sim/uut/uCTRL/data_in" type="array" db_ref_id="1">
      <obj_property name="ElementShortName">data_in[15:0]</obj_property>
      <obj_property name="ObjectShortName">data_in[15:0]</obj_property>
   </wvobject>
   <wvobject fp_name="/system_sim/uut/DP1/data_in" type="array" db_ref_id="1">
      <obj_property name="ElementShortName">data_in[15:0]</obj_property>
      <obj_property name="ObjectShortName">data_in[15:0]</obj_property>
   </wvobject>
   <wvobject fp_name="/system_sim/uut/uCTRL/reg_a" type="array" db_ref_id="1">
      <obj_property name="ElementShortName">reg_a[3:0]</obj_property>
      <obj_property name="ObjectShortName">reg_a[3:0]</obj_property>
   </wvobject>
   <wvobject fp_name="/system_sim/uut/uCTRL/reg_b" type="array" db_ref_id="1">
      <obj_property name="ElementShortName">reg_b[3:0]</obj_property>
      <obj_property name="ObjectShortName">reg_b[3:0]</obj_property>
   </wvobject>
   <wvobject fp_name="/system_sim/uut/uCTRL/op_sel" type="array" db_ref_id="1">
      <obj_property name="ElementShortName">op_sel[3:0]</obj_property>
      <obj_property name="ObjectShortName">op_sel[3:0]</obj_property>
   </wvobject>
   <wvobject fp_name="/system_sim/uut/uCTRL/we" type="logic" db_ref_id="1">
      <obj_property name="ElementShortName">we</obj_property>
      <obj_property name="ObjectShortName">we</obj_property>
   </wvobject>
   <wvobject fp_name="/system_sim/uut/DP1/y" type="array" db_ref_id="1">
      <obj_property name="ElementShortName">y[15:0]</obj_property>
      <obj_property name="ObjectShortName">y[15:0]</obj_property>
   </wvobject>
   <wvobject fp_name="/system_sim/uut/DP1/pc" type="array" db_ref_id="1">
      <obj_property name="ElementShortName">pc[14:0]</obj_property>
      <obj_property name="ObjectShortName">pc[14:0]</obj_property>
   </wvobject>
   <wvobject fp_name="/system_sim/uut/DP1/addr_out_reg" type="array" db_ref_id="1">
      <obj_property name="ElementShortName">addr_out_reg[14:0]</obj_property>
      <obj_property name="ObjectShortName">addr_out_reg[14:0]</obj_property>
   </wvobject>
   <wvobject fp_name="/system_sim/uut/DP1/data_out_reg" type="array" db_ref_id="1">
      <obj_property name="ElementShortName">data_out_reg[15:0]</obj_property>
      <obj_property name="ObjectShortName">data_out_reg[15:0]</obj_property>
   </wvobject>
   <wvobject fp_name="/system_sim/uut/DP1/a" type="array" db_ref_id="1">
      <obj_property name="ElementShortName">a[15:0]</obj_property>
      <obj_property name="ObjectShortName">a[15:0]</obj_property>
   </wvobject>
   <wvobject fp_name="/system_sim/uut/DP1/b" type="array" db_ref_id="1">
      <obj_property name="ElementShortName">b[15:0]</obj_property>
      <obj_property name="ObjectShortName">b[15:0]</obj_property>
   </wvobject>
</wave_config>