Subversion Repositories xucpu

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      <db_ref path="/home/jurgen/Projects/lisp/harddev/system_sim_isim_par.wdb" id="1" type="auto">
         <top_modules>
            <top_module name="std_logic_1164" />
            <top_module name="std_logic_arith" />
            <top_module name="std_logic_signed" />
            <top_module name="std_logic_textio" />
            <top_module name="std_logic_unsigned" />
            <top_module name="system_sim" />
            <top_module name="textio" />
            <top_module name="vcomponents" />
            <top_module name="vital_primitives" />
            <top_module name="vital_timing" />
            <top_module name="vpackage" />
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   <wvobject fp_name="/system_sim/clock" type="logic" db_ref_id="1">
      <obj_property name="ElementShortName">clock</obj_property>
      <obj_property name="ObjectShortName">clock</obj_property>
   </wvobject>
   <wvobject fp_name="/system_sim/uut/uCTRL/clock" type="logic" db_ref_id="1">
      <obj_property name="DisplayName">label</obj_property>
      <obj_property name="ElementShortName">clock</obj_property>
      <obj_property name="ObjectShortName">clock</obj_property>
      <obj_property name="label">uc_clock</obj_property>
   </wvobject>
   <wvobject fp_name="/system_sim/uut/DP1/clock" type="logic" db_ref_id="1">
      <obj_property name="DisplayName">label</obj_property>
      <obj_property name="ElementShortName">clock</obj_property>
      <obj_property name="ObjectShortName">clock</obj_property>
      <obj_property name="label">dp_clock</obj_property>
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   <wvobject fp_name="/system_sim/uut/MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_16_ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram/clka" type="logic" db_ref_id="1">
      <obj_property name="ElementShortName">clka</obj_property>
      <obj_property name="ObjectShortName">clka</obj_property>
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   <wvobject fp_name="/system_sim/uut/MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_8_ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram/clka" type="logic" db_ref_id="1">
      <obj_property name="ElementShortName">clka</obj_property>
      <obj_property name="ObjectShortName">clka</obj_property>
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   <wvobject fp_name="/system_sim/uut/MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_0_ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram/clka" type="logic" db_ref_id="1">
      <obj_property name="ElementShortName">clka</obj_property>
      <obj_property name="ObjectShortName">clka</obj_property>
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   <wvobject fp_name="/system_sim/uut/MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_24_ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram/clka" type="logic" db_ref_id="1">
      <obj_property name="ElementShortName">clka</obj_property>
      <obj_property name="ObjectShortName">clka</obj_property>
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   <wvobject fp_name="/system_sim/uut/MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_29_ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram/clka" type="logic" db_ref_id="1">
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      <obj_property name="ElementShortName">clka</obj_property>
      <obj_property name="ObjectShortName">clka</obj_property>
      <obj_property name="label">mem_clka</obj_property>
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   <wvobject fp_name="/system_sim/reset" type="logic" db_ref_id="1">
      <obj_property name="ElementShortName">reset</obj_property>
      <obj_property name="ObjectShortName">reset</obj_property>
   </wvobject>
   <wvobject fp_name="/system_sim/uut/CLK1/clk_valid" type="logic" db_ref_id="1">
      <obj_property name="ElementShortName">clk_valid</obj_property>
      <obj_property name="ObjectShortName">clk_valid</obj_property>
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   <wvobject fp_name="/system_sim/switch_in" type="array" db_ref_id="1">
      <obj_property name="ElementShortName">switch_in[7:0]</obj_property>
      <obj_property name="ObjectShortName">switch_in[7:0]</obj_property>
   </wvobject>
   <wvobject fp_name="/system_sim/pushb_in" type="array" db_ref_id="1">
      <obj_property name="ElementShortName">pushb_in[4:0]</obj_property>
      <obj_property name="ObjectShortName">pushb_in[4:0]</obj_property>
   </wvobject>
   <wvobject fp_name="/system_sim/led_out" type="array" db_ref_id="1">
      <obj_property name="ElementShortName">led_out[7:0]</obj_property>
      <obj_property name="ObjectShortName">led_out[7:0]</obj_property>
   </wvobject>
   <wvobject fp_name="/system_sim/uut/DP1/pc" type="array" db_ref_id="1">
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      <obj_property name="ObjectShortName">pc[14:0]</obj_property>
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   <wvobject fp_name="/system_sim/uut/uCTRL/reg_a" type="array" db_ref_id="1">
      <obj_property name="ElementShortName">reg_a[3:0]</obj_property>
      <obj_property name="ObjectShortName">reg_a[3:0]</obj_property>
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   <wvobject fp_name="/system_sim/uut/uCTRL/reg_b" type="array" db_ref_id="1">
      <obj_property name="ElementShortName">reg_b[3:0]</obj_property>
      <obj_property name="ObjectShortName">reg_b[3:0]</obj_property>
   </wvobject>
   <wvobject fp_name="/system_sim/uut/uCTRL/op_sel" type="array" db_ref_id="1">
      <obj_property name="ElementShortName">op_sel[3:0]</obj_property>
      <obj_property name="ObjectShortName">op_sel[3:0]</obj_property>
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   <wvobject fp_name="/system_sim/uut/uCTRL/data_in" type="array" db_ref_id="1">
      <obj_property name="ElementShortName">data_in[15:0]</obj_property>
      <obj_property name="ObjectShortName">data_in[15:0]</obj_property>
   </wvobject>
   <wvobject fp_name="/system_sim/uut/uCTRL/memw" type="logic" db_ref_id="1">
      <obj_property name="ElementShortName">memw</obj_property>
      <obj_property name="ObjectShortName">memw</obj_property>
   </wvobject>
   <wvobject fp_name="/system_sim/uut/uCTRL/memr" type="logic" db_ref_id="1">
      <obj_property name="ElementShortName">memr</obj_property>
      <obj_property name="ObjectShortName">memr</obj_property>
   </wvobject>
   <wvobject fp_name="/system_sim/uut/MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_12_ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram/addra[3]" type="logic" db_ref_id="1">
      <obj_property name="ElementShortName">[3]</obj_property>
      <obj_property name="ObjectShortName">addra[3]</obj_property>
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   <wvobject fp_name="/system_sim/uut/MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_29_ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram/doa" type="array" db_ref_id="1">
      <obj_property name="ElementShortName">doa[31:0]</obj_property>
      <obj_property name="ObjectShortName">doa[31:0]</obj_property>
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   <wvobject fp_name="/system_sim/uut/MEM_U0_xst_blk_mem_generator_gnativebmg_native_blk_mem_gen_valid_cstr_ramloop_29_ram_r_s6_init_ram_SP_SIMPLE_PRIM18_ram/wea" type="array" db_ref_id="1">
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      <obj_property name="ObjectShortName">wea[3:0]</obj_property>
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