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[/] [xulalx25soc/] [trunk/] [bench/] [asm/] [cfgtest.s] - Rev 57
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//////////////////////////////////////////////////////////////////////////////// // // Filename: cfgtest.s // // Project: XuLA2 board // // Purpose: To test whether or not the SPARTAN6_ICAPE interface works with // the wbicape6.v / wbicapesimple.v modules. // // Normally, I'd do this test using wbregs only. In this case, that's // not possible. wbregs requires the use of the JTAG port for the XuLA // board. Further, JTAG and ICAPE cannot be used at the same time. So // our goal instead will be to use wbregs and ziprun to start this program, // to disconnect (i.e. stop using wbregs and ziprun, just leaving the CPU // to run), to wait for an RTC alarm, to trigger the configuration port // scope, and then to see how we did. That's a lot, but doing things in // order is what a CPU is for--so let's see how we do. // // // Creator: Dan Gisselquist, Ph.D. // Gisselquist Technology, LLC // //////////////////////////////////////////////////////////////////////////////// // // Copyright (C) 2015, Gisselquist Technology, LLC // // This program is free software (firmware): you can redistribute it and/or // modify it under the terms of the GNU General Public License as published // by the Free Software Foundation, either version 3 of the License, or (at // your option) any later version. // // This program is distributed in the hope that it will be useful, but WITHOUT // ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License // for more details. // // License: GPL, v3, as defined and found on www.gnu.org, // http://www.gnu.org/licenses/gpl.html // // //////////////////////////////////////////////////////////////////////////////// // // #include "dev.i" #include "sys.i" master_entry: BRA end_of_data external_data: cfg_result: WORD 0 status: WORD 0 end_of_data: ; Set up our stacks--though I don't think we'll need them MOV sys_stack(PC),SP MOV user_stack(PC),uSP ; ; Clear our registers CLR R0 CLR R1 CLR R2 CLR R3 CLR R4 CLR R5 CLR R6 CLR R7 CLR R8 CLR R9 CLR R10 CLR R11 MOV R0,uR0 MOV R0,uR1 MOV R0,uR2 MOV R0,uR3 MOV R0,uR4 MOV R0,uR5 MOV R0,uR6 MOV R0,uR7 MOV R0,uR8 MOV R0,uR9 MOV R0,uR10 MOV R0,uR12 ; ; Reset and prime our scope LDI dev.cfgscope,R12 LDI 0x03fc,R0 STO R0,(R12) ; ; Wait on an alarm LDI sys.bus,R12 LDI 0x7fffffff,R0 // Clear and disable all interrupts STO R0,(R12) ; LDI RTCINTEN|0x0ffff,R0 // Enable the RTC interrupt LDI 0x8080ffff,R0 STO R0,(R12) ; MOV user_idle(PC),uPC RTU ; LDI 0x0080ffff,R0 STO R0,(R12) ; MOV user_entry(PC),uPC MOV user_stack(PC),uSP ; RTU ; HALT HALT BUSY HALT user_idle: WAIT BRA user_idle user_entry: LDI dev.cfg,R1 LOD (R1),R0 ADD 5,R0 STO R0,cfg_result(PC) LDI 14,R0 LDI dev.cfg.cmd,R1 STO R0,(R1) NOOP TRAP 0 user_end_of_stack: FILL 512,0 user_stack: sys_end_of_stack: FILL 512,0 sys_stack: WORD 0 ; ;
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