OpenCores
URL https://opencores.org/ocsvn/xulalx25soc/xulalx25soc/trunk

Subversion Repositories xulalx25soc

[/] [xulalx25soc/] [trunk/] [sw/] [cfgscope.cpp] - Rev 15

Go to most recent revision | Compare with Previous | Blame | View Log

//
//
// Filename: 	cfgscope.cpp
//
// Project:	FPGA library development (Basys-3 development board)
//
// Purpose:	To read out, and decompose, the results of the wishbone scope
//		as applied to the ICAPE2 interaction.
//
// Creator:	Dan Gisselquist
//		Gisselquist Tecnology, LLC
//
// Copyright:	2015
//
//
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <strings.h>
#include <ctype.h>
#include <string.h>
#include <signal.h>
#include <assert.h>
 
#include "port.h"
#include "llcomms.h"
#include "regdefs.h"
 
#define	WBSCOPE		R_CFGSCOPE
#define	WBSCOPEDATA	R_CFGSCOPED
 
FPGA	*m_fpga;
void	closeup(int v) {
	m_fpga->kill();
	exit(0);
}
 
unsigned brev(const unsigned v) {
	unsigned int r, a;
	a = v;
	r = 0;
	for(int i=0; i<8; i++) {
		r <<= 1;
		r |= (a&1);
		a >>= 1;
	} return r;
}
 
unsigned wrev(const unsigned v) {
	unsigned r = brev(v&0x0ff);
	r |= brev((v>>8)&0x0ff)<<8;
	return r;
}
 
int main(int argc, char **argv) {
	FPGAOPEN(m_fpga);
 
	signal(SIGSTOP, closeup);
	signal(SIGHUP, closeup);
 
	unsigned	v, lgln, scoplen;
	printf("Attempting to read address %08x\n", WBSCOPE);
	v = m_fpga->readio(WBSCOPE);
	if (0x60000000 != (v & 0x60000000)) {
		printf("Scope is not yet ready:\n");
		printf("\tRESET:\t\t%s\n", (v&0x80000000)?"Ongoing":"Complete");
		printf("\tSTOPPED:\t%s\n", (v&0x40000000)?"Yes":"No");
		printf("\tTRIGGERED:\t%s\n", (v&0x20000000)?"Yes":"No");
		printf("\tPRIMED:\t\t%s\n", (v&0x10000000)?"Yes":"No");
		printf("\tMANUAL:\t\t%s\n", (v&0x08000000)?"Yes":"No");
		printf("\tDISABLED:\t%s\n", (v&0x04000000)?"Yes":"No");
		printf("\tZERO:\t\t%s\n", (v&0x02000000)?"Yes":"No");
		exit(0);
	} else printf("SCOPD = %08x\n", v);
 
	lgln = (v>>20) & 0x1f;
	scoplen = (1<<lgln);
 
	DEVBUS::BUSW	*buf;
	buf = new DEVBUS::BUSW[scoplen];
 
	if (false) {
		printf("Attempting vector read\n");
		m_fpga->readz(WBSCOPEDATA, scoplen, buf);
 
		printf("Vector read complete\n");
	} else {
		for(unsigned int i=0; i<scoplen; i++)
			buf[i] = m_fpga->readio(WBSCOPEDATA);
	}
 
	for(unsigned int i=0; i<scoplen; i++) {
		if ((i>0)&&(buf[i] == buf[i-1])&&
				(i<scoplen-1)&&(buf[i] == buf[i+1]))
			continue;
		printf("%6d %08x:", i, buf[i]);
		printf("S(%x) ", (buf[i]>>27)&0x0f);
		if (buf[i] & 0x40000000)
			printf("W "); else printf("R ");
		printf("WB(%s%s%s%s%s)-%s%s%s%s%s",
			(buf[i]&0x2000000)?"CYC":"   ",
			(buf[i]&0x1000000)?"STB":"   ",
			(buf[i]&0x0800000)?"WE":"  ",
			(buf[i]&0x0400000)?"ACK":"   ",
			(buf[i]&0x0200000)?"STL":"   ",
			(buf[i]&0x0100000)?"EDG":"   ",
			(buf[i]&0x0080000)?"CLK":"   ",
			(buf[i]&0x0040000)?"   ":"CEn",
			(buf[i]&0x0020000)?"BSY":"   ",
			(buf[i]&0x0010000)?"  ":"WE");
		if (buf[i]&0x10000)
			printf("->"); // Read
		else	printf("<-");
		printf(" %04x\n", wrev(buf[i] & 0x0ffff));
	}
 
	if (m_fpga->poll()) {
		printf("FPGA was interrupted\n");
		m_fpga->clear();
		m_fpga->writeio(R_ICONTROL, SCOPEN);
	}
	delete	m_fpga;
}
 
 

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.